SAMOS 2001
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Table of Contents SAMOS Workshop 2009

Koen Bertels, Nikitas Dimopoulos, Cristina Silvano and Stephan Wong Eds.
Lecture Notes in Computer Science
Volume 5657, 2009, DOI: 10.1007/978-3-642-03138-0

Front matter Author Index Search

Springer

 

Beachnote

 

 

 

What Else Is Broken? Can We Fix It?

PAGE

1

2009-WS-01

Yale Patt

Architectures for Multimedia

 

 

 

Programmable and Scalable Architecture for Graphics Processing Units

PAGES

2--11

 

Carlos S. de la Lama, Pekka Jääskeläinen, Jarmo Takala

The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors

PAGES

12--23

 

Paul M. Carpenter, Alex Ramirez, Eduard Ayguade

CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey

PAGES

24--35

 

Yahya Jan, Lech Jozwiak

Programmable Accelerators for Reconfigurable Video Decoder

PAGES

36--47

 

Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silven 

Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study

PAGES

48--57

 

Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor 

Multiple Description Scalable Coding for Video Transmission over Unreliable Networks

PAGES

58--67

 

Roya Choupani, Stephan Wong, Mehmet R. Tolun

Multi/Many Cores Architectures

 

 

 

Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC

PAGES

68--77

 

Sascha Uhrig

Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture

PAGES

78--87

 

Roberto Giorgi, Zdravko Popovic, Nikola Puzovic

Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management

PAGES

88--97

 

Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi

A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA

PAGES

98--107

 

Christian Schäck, Wolfgang Heenes, Rolf Hoffmann

VLSI Architectures Design

 

 

 

Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing

PAGES

108--117

 

Nainesh Agarwal, Nikitas J. Dimopoulos

Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata

PAGES

118--127

 

Ismo Hänninen, Jarmo Takala

Prediction in Dynamic SDRAM Controller Policies

PAGES

128--138

 

Ying Xu, Aabhas S. Agarwal, Brian T. Davis

Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI

PAGES

139--148

 

Shinichi Kato, Minoru Watanabe

Architecture Modeling and Exploration Tools

 

 

 

Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration

PAGES

149--160

 

Toktam Taghavi, Mark Thompson, Andy D. Pimentel

Modeling Scalable SIMD DSPs in LISA

PAGES

161--170

 

Peter Westermann, Hartmut Schröder

NoGAP: A Micro Architecture Construction Framework

PAGES

171--180

 

Per Karlström, Dake Liu

A Comparison of NoTA and GENESYS

PAGES

181--192

 

Bernhard Huber, Roman Obermaisser

Special Session 1: Instruction-Set Customization

 

 

 

Introduction to Instruction-Set Customization

PAGE

193

2009-WS-20

Carlo Galuzzi

Constraint-Driven Identification of Application Specific Instructions in the DURASE System

PAGES

194--203

 

Kevin Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot

A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs)

PAGES

204--214

 

Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr

Runtime Adaptive Extensible Embedded Processors — A Survey

PAGES

215--225

 

Huynh Phung Huynh, Tulika Mitra

Special Session 2: The Future of Reconfigurable Computing and Processor Architectures

 

 

 

Introduction to the Future of Reconfigurable Computing and Processor Architectures

PAGE

226

2009-WS-24

Luigi Carro, Stephan Wong

An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems

PAGES

227--236

 

Rainer Buchty, Mario Kicherer, David Kramer, Wolfgang Karl

Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study

PAGES

237--246

 

Frederico Pratas, Leonel Sousa

Reconfigurable Multicore Server Processors for Low Power Operation

PAGES

247--254

 

Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor Mudge

Reconfigurable Computing in the New Age of Parallelism

PAGES

255--262

 

Walid A. Najjar, Jason Villarreal

Reconfigurable Multithreading Architectures: A Survey

PAGES

263--274

 

Pavel G. Zaykov, Georgi Kuzmanov, Georgi N. Gaydadjiev

Special Session 3: Mastering Cell BE and GPU Execution Platforms

 

 

 

Introduction to Mastering Cell BE and GPU Execution Platforms

PAGES

275--276

2009-WS-30

Ed F. Deprettere, Ana L. Varbanescu

Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors

PAGES

277--288

 

Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich

Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs

PAGES

289--297

 

Alexander Monakov, Arutyun Avetisyan

Experiences with Cell-BE and GPU for Tomography

PAGES

298--307

 

Sander van der Maar, Kees Joost Batenburg, Jan Sijbers

Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell

PAGES

308--317

 

Dmitry Nadezhkin, Sjoerd Meijer, Todor Stefanov, Ed F. Deprettere

Exploiting Locality on the Cell/B.E. through Bypassing

PAGES

318--328

 

Pieter Bellens, Josep M. Perez, Rosa M. Badia, Jesus Labarta

Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System

PAGES

329--339

 

Cédric Augonnet, Samuel Thibault, Raymond Namyst, Maik Nijhuis