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Table of Contents SAMOS Workshop 2009Koen Bertels, Nikitas Dimopoulos, Cristina Silvano and Stephan Wong Eds.
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Beachnote |
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What Else Is Broken? Can We Fix It? |
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1 |
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Yale Patt |
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Architectures for Multimedia |
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Programmable and Scalable Architecture for Graphics Processing Units |
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2--11 |
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Carlos S. de la Lama, Pekka Jääskeläinen, Jarmo Takala |
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The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors |
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12--23 |
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Paul M. Carpenter, Alex Ramirez, Eduard Ayguade |
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CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey |
PAGES |
24--35 |
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Yahya Jan, Lech Jozwiak |
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Programmable Accelerators for Reconfigurable Video Decoder |
PAGES |
36--47 |
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Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silven |
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Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study |
PAGES |
48--57 |
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Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor |
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Multiple Description Scalable Coding for Video Transmission over Unreliable Networks |
PAGES |
58--67 |
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Roya Choupani, Stephan Wong, Mehmet R. Tolun |
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Multi/Many Cores Architectures |
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Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC |
PAGES |
68--77 |
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Sascha Uhrig |
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Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture |
PAGES |
78--87 |
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Roberto Giorgi, Zdravko Popovic, Nikola Puzovic |
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Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management |
PAGES |
88--97 |
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Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi |
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A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA |
PAGES |
98--107 |
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Christian Schäck, Wolfgang Heenes, Rolf Hoffmann |
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VLSI Architectures Design |
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Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing |
PAGES |
108--117 |
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Nainesh Agarwal, Nikitas J. Dimopoulos |
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Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata |
PAGES |
118--127 |
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Ismo Hänninen, Jarmo Takala |
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Prediction in Dynamic SDRAM Controller Policies |
PAGES |
128--138 |
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Ying Xu, Aabhas S. Agarwal, Brian T. Davis |
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Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI |
PAGES |
139--148 |
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Shinichi Kato, Minoru Watanabe |
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Architecture Modeling and Exploration Tools |
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Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration |
PAGES |
149--160 |
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Toktam Taghavi, Mark Thompson, Andy D. Pimentel |
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Modeling Scalable SIMD DSPs in LISA |
PAGES |
161--170 |
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Peter Westermann, Hartmut Schröder |
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NoGAP: A Micro Architecture Construction Framework |
PAGES |
171--180 |
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Per Karlström, Dake Liu |
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A Comparison of NoTA and GENESYS |
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181--192 |
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Bernhard Huber, Roman Obermaisser |
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Special Session 1: Instruction-Set Customization |
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Introduction to Instruction-Set Customization |
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193 |
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Carlo Galuzzi |
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Constraint-Driven Identification of Application Specific Instructions in the DURASE System |
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194--203 |
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Kevin Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot |
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A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) |
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204--214 |
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Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
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Runtime Adaptive Extensible Embedded Processors — A Survey |
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215--225 |
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Huynh Phung Huynh, Tulika Mitra |
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Special Session 2: The Future of Reconfigurable Computing and Processor Architectures |
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Introduction to the Future of Reconfigurable Computing and Processor Architectures |
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226 |
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Luigi Carro, Stephan Wong |
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An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems |
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227--236 |
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Rainer Buchty, Mario Kicherer, David Kramer, Wolfgang Karl |
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Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study |
PAGES |
237--246 |
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Frederico Pratas, Leonel Sousa |
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Reconfigurable Multicore Server Processors for Low Power Operation |
PAGES |
247--254 |
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Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor Mudge |
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Reconfigurable Computing in the New Age of Parallelism |
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255--262 |
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Walid A. Najjar, Jason Villarreal |
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Reconfigurable Multithreading Architectures: A Survey |
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263--274 |
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Pavel G. Zaykov, Georgi Kuzmanov, Georgi N. Gaydadjiev |
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Special Session 3: Mastering Cell BE and GPU Execution Platforms |
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Introduction to Mastering Cell BE and GPU Execution Platforms |
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275--276 |
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Ed F. Deprettere, Ana L. Varbanescu |
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Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors |
PAGES |
277--288 |
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Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich |
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Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs |
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289--297 |
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Alexander Monakov, Arutyun Avetisyan |
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Experiences with Cell-BE and GPU for Tomography |
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298--307 |
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Sander van der Maar, Kees Joost Batenburg, Jan Sijbers |
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Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell |
PAGES |
308--317 |
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Dmitry Nadezhkin, Sjoerd Meijer, Todor Stefanov, Ed F. Deprettere |
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Exploiting Locality on the Cell/B.E. through Bypassing |
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318--328 |
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Pieter Bellens, Josep M. Perez, Rosa M. Badia, Jesus Labarta |
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Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System |
PAGES |
329--339 |
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Cédric Augonnet, Samuel Thibault, Raymond Namyst, Maik Nijhuis |