Publication Filter Generator

Here, you can search for papers published in the SAMOS Workshops and SAMOS Conferences from 2001. You can search either by name, and/or by year, and/or by specific keywords in the title of the paper/session. For each document in the table, a link to download the file in pdf format is included at the end of the corresponding row.

Name
Year
Title of the publicationa
Author(s) of the publicationb
Sessionc
Download (PDF)
Avasare, Prabhat
2001
Desm-E-leoign of Can, a Run-Time Reconfigurable Web Camera Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest  Applications 2001-WS-16
Bednara, Marcus
2001
Generation of Distributed Loop Control Marcus Bednara, Frank Hannig, Jürgen Teich   Compiler and Mapping Technology 2001-WS-09
Bhattacharya, Bishnupriya
2001
Consistency Analysis of Reconfigurable Dataflow Specifications Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya System-Level Design and Simulation 2001-WS-01
Bhattacharyya, Shuvra S.
2001
Consistency Analysis of Reconfigurable Dataflow Specifications Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya System-Level Design and Simulation 2001-WS-01
Coene, Paul
2001
Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest  Applications 2001-WS-16
Coffland, Joe E.
2001
Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems Andy D. Pimentel, Simon Polstra, Frank P. Terpstra, A. W. van Halderen, Joe E. Coffland, L.O. Hertzberger  System-Level Design and Simulation 2001-WS-04
Cotofana, Sorin Dan
2001
Microcoded Reconfigurable Embedded Processors: Current Developments Stephan Wong, Stamatis Vassiliadis, Sorin Dan Cotofana   Embedded Processors and Architectures 2001-WS-12
Cotofana, Sorin Dan
2001
A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees Vissers Embedded Processors and Architectures 2001-WS-13
Decneut, Stijn
2001
Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest  Applications 2001-WS-16
Deprettere, Ed F.
2001
A Methodology to Design Programmable Embedded Systems: The Y-Chart Approach Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees Vissers  System-Level Design and Simulation 2001-WS-02
Deprettere, Ed F.
2001
Translating Imperative Affine Nested Loop Programs into Process Networks Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis   Compiler and Mapping Technology 2001-WS-06
Desmet, Dirk
2001
Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest  Applications 2001-WS-16
Dey, Sujit
2001
Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication Clark N. Taylor, Debashis Panigrahi, Sujit Dey   Embedded Processors and Architectures 2001-WS-15
Ernst, Rolf
2001
Flexibility/Cost-Tradeoffs of Platform-Based Systems Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst  System-Level Design and Simulation 2001-WS-03
Freimann, A.
2001
Processor Architectures for Multimedia Applications Peter Pirsch, A. Freimann, C. Klar, Jens Peter Wittenburg   Embedded Processors and Architectures 2001-WS-11
Glossner, John
2001
A Java-Enabled DSP John Glossner, Michael Schulte, Stamatis Vassiliadis Applications 2001-WS-18
Hannig, Frank
2001
Generation of Distributed Loop Control Marcus Bednara, Frank Hannig, Jürgen Teich   Compiler and Mapping Technology 2001-WS-09
Haubelt, Christian
2001
Flexibility/Cost-Tradeoffs of Platform-Based Systems Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst  System-Level Design and Simulation 2001-WS-03
Hendrickx, Filip
2001
Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest  Applications 2001-WS-16
Hertzberger, L.O.
2001
Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems Andy D. Pimentel, Simon Polstra, Frank P. Terpstra, A. W. van Halderen, Joe E. Coffland, L.O. Hertzberger  System-Level Design and Simulation 2001-WS-04
Irwin, James
2001
Caches with Compositional Performance Henk Muller, Dan Page, James Irwin, David May   Embedded Processors and Architectures 2001-WS-14
Kienhuis, Bart
2001
A Methodology to Design Programmable Embedded Systems: The Y-Chart Approach Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees Vissers  System-Level Design and Simulation 2001-WS-02
Kienhuis, Bart
2001
Translating Imperative Affine Nested Loop Programs into Process Networks Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis   Compiler and Mapping Technology 2001-WS-06
Kisuki, T.
2001
Iterative Compilation Peter M. W. Knijnenburg, T. Kisuki, M. F. P. O’Boyle   Compiler and Mapping Technology 2001-WS-10
Klar, C.
2001
Processor Architectures for Multimedia Applications Peter Pirsch, A. Freimann, C. Klar, Jens Peter Wittenburg   Embedded Processors and Architectures 2001-WS-11
Knijnenburg, Peter M. W.
2001
Iterative Compilation Peter M. W. Knijnenburg, T. Kisuki, M. F. P. O’Boyle   Compiler and Mapping Technology 2001-WS-10
Kuzmanov, Georgi
2001
A 2D Addressing Mode for Multimedia Applications Georgi Kuzmanov, Stamatis Vassiliadis, Jos T. J. van Eijndhoven Applications 2001-WS-17
Lieverse, Paul
2001
An Overview of Methodologies and Tools in the Field of System-Level Design Vladimir D. Zivkovic, Paul Lieverse  System-Level Design and Simulation 2001-WS-05
Marescaux, Théodore
2001
Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest  Applications 2001-WS-16
May, David
2001
Caches with Compositional Performance Henk Muller, Dan Page, James Irwin, David May   Embedded Processors and Architectures 2001-WS-14
Mignolet, Jean-Yves
2001
Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest  Applications 2001-WS-16
Muller, Henk
2001
Caches with Compositional Performance Henk Muller, Dan Page, James Irwin, David May   Embedded Processors and Architectures 2001-WS-14
O’Boyle, M. F. P.
2001
Iterative Compilation Peter M. W. Knijnenburg, T. Kisuki, M. F. P. O’Boyle   Compiler and Mapping Technology 2001-WS-10
Page, Dan
2001
Caches with Compositional Performance Henk Muller, Dan Page, James Irwin, David May   Embedded Processors and Architectures 2001-WS-14
Panigrahi, Debashis
2001
Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication Clark N. Taylor, Debashis Panigrahi, Sujit Dey   Embedded Processors and Architectures 2001-WS-15
Pasko, Robert
2001
Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest  Applications 2001-WS-16
Pimentel, Andy D.
2001
Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems Andy D. Pimentel, Simon Polstra, Frank P. Terpstra, A. W. van Halderen, Joe E. Coffland, L.O. Hertzberger  System-Level Design and Simulation 2001-WS-04
Pirsch, Peter
2001
Processor Architectures for Multimedia Applications Peter Pirsch, A. Freimann, C. Klar, Jens Peter Wittenburg   Embedded Processors and Architectures 2001-WS-11
Polstra, Simon
2001
Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems Andy D. Pimentel, Simon Polstra, Frank P. Terpstra, A. W. van Halderen, Joe E. Coffland, L.O. Hertzberger  System-Level Design and Simulation 2001-WS-04
Quinton, Patrice
2001
Structured Scheduling of Recurrence Equations: Theory and Practice Patrice Quinton, Tanguy Risset  Compiler and Mapping Technology 2001-WS-07
Richter, Kai
2001
Flexibility/Cost-Tradeoffs of Platform-Based Systems Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst  System-Level Design and Simulation 2001-WS-03
Rijpkema, Edwin
2001
Translating Imperative Affine Nested Loop Programs into Process Networks Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis   Compiler and Mapping Technology 2001-WS-06
Risset, Tanguy
2001
Structured Scheduling of Recurrence Equations: Theory and Practice Patrice Quinton, Tanguy Risset  Compiler and Mapping Technology 2001-WS-07
Schaumont, Patrick
2001
Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest  Applications 2001-WS-16
Schulte, Michael
2001
A Java-Enabled DSP John Glossner, Michael Schulte, Stamatis Vassiliadis Applications 2001-WS-18
Sima, Mihai
2001
A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees Vissers Embedded Processors and Architectures 2001-WS-13
Taylor, Clark N.
2001
Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication Clark N. Taylor, Debashis Panigrahi, Sujit Dey   Embedded Processors and Architectures 2001-WS-15
Teich, Jürgen
2001
Flexibility/Cost-Tradeoffs of Platform-Based Systems Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst  System-Level Design and Simulation 2001-WS-03
Teich, Jürgen
2001
Exact Partitioning of Affine Dependence Algorithms Jürgen Teich, Lothar Thiele  Compiler and Mapping Technology 2001-WS-08
Teich, Jürgen
2001
Generation of Distributed Loop Control Marcus Bednara, Frank Hannig, Jürgen Teich   Compiler and Mapping Technology 2001-WS-09
Terpstra, Frank P.
2001
Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems Andy D. Pimentel, Simon Polstra, Frank P. Terpstra, A. W. van Halderen, Joe E. Coffland, L.O. Hertzberger  System-Level Design and Simulation 2001-WS-04
Thiele, Lothar
2001
Exact Partitioning of Affine Dependence Algorithms Jürgen Teich, Lothar Thiele  Compiler and Mapping Technology 2001-WS-08
van der Wolf, Pieter
2001
A Methodology to Design Programmable Embedded Systems: The Y-Chart Approach Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees Vissers  System-Level Design and Simulation 2001-WS-02
van Eijndhoven, Jos T. J.
2001
A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees Vissers Embedded Processors and Architectures 2001-WS-13
van Eijndhoven, Jos T. J.
2001
A 2D Addressing Mode for Multimedia Applications Georgi Kuzmanov, Stamatis Vassiliadis, Jos T. J. van Eijndhoven Applications 2001-WS-17
van Halderen, A. W.
2001
Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems Andy D. Pimentel, Simon Polstra, Frank P. Terpstra, A. W. van Halderen, Joe E. Coffland, L.O. Hertzberger  System-Level Design and Simulation 2001-WS-04
Vassiliadis, Stamatis
2001
Microcoded Reconfigurable Embedded Processors: Current Developments Stephan Wong, Stamatis Vassiliadis, Sorin Dan Cotofana   Embedded Processors and Architectures 2001-WS-12
Vassiliadis, Stamatis
2001
A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees Vissers Embedded Processors and Architectures 2001-WS-13
Vassiliadis, Stamatis
2001
A 2D Addressing Mode for Multimedia Applications Georgi Kuzmanov, Stamatis Vassiliadis, Jos T. J. van Eijndhoven Applications 2001-WS-17
Vassiliadis, Stamatis
2001
A Java-Enabled DSP John Glossner, Michael Schulte, Stamatis Vassiliadis Applications 2001-WS-18
Verkest, Diederik
2001
Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest  Applications 2001-WS-16
Vissers, Kees
2001
A Methodology to Design Programmable Embedded Systems: The Y-Chart Approach Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees Vissers  System-Level Design and Simulation 2001-WS-02
Vissers, Kees
2001
A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees Vissers Embedded Processors and Architectures 2001-WS-13
Wittenburg, Jens Peter
2001
Processor Architectures for Multimedia Applications Peter Pirsch, A. Freimann, C. Klar, Jens Peter Wittenburg   Embedded Processors and Architectures 2001-WS-11
Wong, Stephan
2001
Microcoded Reconfigurable Embedded Processors: Current Developments Stephan Wong, Stamatis Vassiliadis, Sorin Dan Cotofana   Embedded Processors and Architectures 2001-WS-12
Zivkovic, Vladimir D.
2001
An Overview of Methodologies and Tools in the Field of System-Level Design Vladimir D. Zivkovic, Paul Lieverse  System-Level Design and Simulation 2001-WS-05
Alliot, Sylvain
2002
A Scalable platform for large scale array signal processing systems specification and prototyping Sylvain Alliot, Ed F. Deprettere Modeling & Simulation 2002-WS-05
Bhattacharyya, Shuvra S.
2002
Goal-Driven Reconfiguration of Polymorphous Architectures Sumit Lohani, Shuvra S. Bhattacharyya Reconfigurable Architecture 2002-WS-08
Cheung, Peter Y.K.
2002
Customising Flexible Instruction Processors: A Tutorial Introduction Shay Ping Seng, Wayne Luk, Peter Y.K. Cheung Processors 2002-WS-09
Coffland, Joe E.
2002
Modeling of Intra-task Parallelism in Sesame Andy D. Pimentel, Frank P. Terpstra, Simon Polstra, Joe E. Coffland  Modeling & Simulation 2002-WS-01
Cotofana, Sorin Dan
2002
Future Directions of (Programmable and Reconfigurable) Embedded Processors Stephan Wong, Stamatis Vassiliadis, Sorin Dan Cotofana Reconfigurable Architecture 2002-WS-06
Cotofana, Sorin Dan
2002
Entropy Decoding on TriMedia/CPU64 Mihai Sima, Evert-Jan Pol, Jos T. J. van Eijndhoven, Sorin Dan Cotofana, Stamatis Vassiliadis  Processors 2002-WS-10
Deprettere, Ed F.
2002
Realizations of the Extended Linearization Model in the Compaan Tool Chain Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere Modeling & Simulation 2002-WS-04
Deprettere, Ed F.
2002
A Scalable platform for large scale array signal processing systems specification and prototyping Sylvain Alliot, Ed F. Deprettere Modeling & Simulation 2002-WS-05
Derrien, Steven
2002
Automatic Synthesis of Efficient Interfaces from Compiled Regular Architectures Steven Derrien, Anne-Claire Guillou, Patrice Quinton, Tanguy Risset, Charles Wagner  Modeling & Simulation 2002-WS-03
Glossner, John
2002
Automatic VHDL Model Generation of Parameterized FIR Filters E. George Walters III, John Glossner, Michael Schulte Processors 2002-WS-13
Guevorkian, David
2002
Highly Efficient Scalable Parallel-Pipelined Architectures for Discrete Wavelet Transforms David Guevorkian, Petri Liuha, Aki Launiainen, Ville Lappalainen  Processors 2002-WS-12
Guillou, Anne-Claire
2002
Automatic Synthesis of Efficient Interfaces from Compiled Regular Architectures Steven Derrien, Anne-Claire Guillou, Patrice Quinton, Tanguy Risset, Charles Wagner  Modeling & Simulation 2002-WS-03
Hannig, Frank
2002
Energy Estimation for Piecewise Regular Processor Arrays Frank Hannig, Jürgen Teich Modeling & Simulation 2002-WS-02
Järvinen, Tuomas
2002
Stride Permutation Access in Interleaved Memory Systems Jarmo Takala, Tuomas Järvinen Processors 2002-WS-11
Kienhuis, Bart
2002
Realizations of the Extended Linearization Model in the Compaan Tool Chain Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere Modeling & Simulation 2002-WS-04
Lagadec, Loïc
2002
A high level synthesis framework for reconfigurable architectures Loïc Lagadec, Bernard Pottier, Oscar Villellas-Guillen Reconfigurable Architecture 2002-WS-07
Lappalainen, Ville
2002
Highly Efficient Scalable Parallel-Pipelined Architectures for Discrete Wavelet Transforms David Guevorkian, Petri Liuha, Aki Launiainen, Ville Lappalainen  Processors 2002-WS-12
Launiainen, Aki
2002
Highly Efficient Scalable Parallel-Pipelined Architectures for Discrete Wavelet Transforms David Guevorkian, Petri Liuha, Aki Launiainen, Ville Lappalainen  Processors 2002-WS-12
Liuha, Petri
2002
Highly Efficient Scalable Parallel-Pipelined Architectures for Discrete Wavelet Transforms David Guevorkian, Petri Liuha, Aki Launiainen, Ville Lappalainen  Processors 2002-WS-12
Lohani, Sumit
2002
Goal-Driven Reconfiguration of Polymorphous Architectures Sumit Lohani, Shuvra S. Bhattacharyya Reconfigurable Architecture 2002-WS-08
Luk, Wayne
2002
Customising Flexible Instruction Processors: A Tutorial Introduction Shay Ping Seng, Wayne Luk, Peter Y.K. Cheung Processors 2002-WS-09
Pimentel, Andy D.
2002
Modeling of Intra-task Parallelism in Sesame Andy D. Pimentel, Frank P. Terpstra, Simon Polstra, Joe E. Coffland  Modeling & Simulation 2002-WS-01
Pol, Evert-Jan
2002
Entropy Decoding on TriMedia/CPU64 Mihai Sima, Evert-Jan Pol, Jos T. J. van Eijndhoven, Sorin Dan Cotofana, Stamatis Vassiliadis  Processors 2002-WS-10
Polstra, Simon
2002
Modeling of Intra-task Parallelism in Sesame Andy D. Pimentel, Frank P. Terpstra, Simon Polstra, Joe E. Coffland  Modeling & Simulation 2002-WS-01
Pottier, Bernard
2002
A high level synthesis framework for reconfigurable architectures Loïc Lagadec, Bernard Pottier, Oscar Villellas-Guillen Reconfigurable Architecture 2002-WS-07
Quinton, Patrice
2002
Automatic Synthesis of Efficient Interfaces from Compiled Regular Architectures Steven Derrien, Anne-Claire Guillou, Patrice Quinton, Tanguy Risset, Charles Wagner  Modeling & Simulation 2002-WS-03
Risset, Tanguy
2002
Automatic Synthesis of Efficient Interfaces from Compiled Regular Architectures Steven Derrien, Anne-Claire Guillou, Patrice Quinton, Tanguy Risset, Charles Wagner  Modeling & Simulation 2002-WS-03
Schulte, Michael
2002
Automatic VHDL Model Generation of Parameterized FIR Filters E. George Walters III, John Glossner, Michael Schulte Processors 2002-WS-13
Seng, Shay Ping
2002
Customising Flexible Instruction Processors: A Tutorial Introduction Shay Ping Seng, Wayne Luk, Peter Y.K. Cheung Processors 2002-WS-09
Sima, Mihai
2002
Entropy Decoding on TriMedia/CPU64 Mihai Sima, Evert-Jan Pol, Jos T. J. van Eijndhoven, Sorin Dan Cotofana, Stamatis Vassiliadis  Processors 2002-WS-10
Takala, Jarmo
2002
Stride Permutation Access in Interleaved Memory Systems Jarmo Takala, Tuomas Järvinen Processors 2002-WS-11
Teich, Jürgen
2002
Energy Estimation for Piecewise Regular Processor Arrays Frank Hannig, Jürgen Teich Modeling & Simulation 2002-WS-02
Terpstra, Frank P.
2002
Modeling of Intra-task Parallelism in Sesame Andy D. Pimentel, Frank P. Terpstra, Simon Polstra, Joe E. Coffland  Modeling & Simulation 2002-WS-01
Turjan, Alexandru
2002
Realizations of the Extended Linearization Model in the Compaan Tool Chain Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere Modeling & Simulation 2002-WS-04
van Eijndhoven, Jos T. J.
2002
Entropy Decoding on TriMedia/CPU64 Mihai Sima, Evert-Jan Pol, Jos T. J. van Eijndhoven, Sorin Dan Cotofana, Stamatis Vassiliadis  Processors 2002-WS-10
Vassiliadis, Stamatis
2002
Future Directions of (Programmable and Reconfigurable) Embedded Processors Stephan Wong, Stamatis Vassiliadis, Sorin Dan Cotofana Reconfigurable Architecture 2002-WS-06
Vassiliadis, Stamatis
2002
Entropy Decoding on TriMedia/CPU64 Mihai Sima, Evert-Jan Pol, Jos T. J. van Eijndhoven, Sorin Dan Cotofana, Stamatis Vassiliadis  Processors 2002-WS-10
Villellas-Guillen, Oscar
2002
A high level synthesis framework for reconfigurable architectures Loïc Lagadec, Bernard Pottier, Oscar Villellas-Guillen Reconfigurable Architecture 2002-WS-07
Wagner, Charles
2002
Automatic Synthesis of Efficient Interfaces from Compiled Regular Architectures Steven Derrien, Anne-Claire Guillou, Patrice Quinton, Tanguy Risset, Charles Wagner  Modeling & Simulation 2002-WS-03
Walters III, E. George
2002
Automatic VHDL Model Generation of Parameterized FIR Filters E. George Walters III, John Glossner, Michael Schulte Processors 2002-WS-13
Wong, Stephan
2002
Future Directions of (Programmable and Reconfigurable) Embedded Processors Stephan Wong, Stamatis Vassiliadis, Sorin Dan Cotofana Reconfigurable Architecture 2002-WS-06
Ascheid, Gerd
2003
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr   Architectures and Implementation 2003-WS-15
Ayguadé, Eduard
2003
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero  Architectures and Implementation 2003-WS-10
Benoit, Pascal
2003
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon   Architectures and Implementation 2003-WS-14
Bertels, Koen
2003
The Molen Programming Paradigm Stamatis Vassiliadis, Georgi N. Gaydadjiev, Koen Bertels, Elena Moscu Panainte  Reconfigurable Computing 2003-WS-01
Blanc, Frédéric
2003
RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems Stéphane Chevobbe, Nicolas Ventroux, Frédéric Blanc, Thierry Collette  Reconfigurable Computing 2003-WS-03
Cambon, Gaston
2003
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon   Architectures and Implementation 2003-WS-14
Chevobbe, Stéphane
2003
RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems Stéphane Chevobbe, Nicolas Ventroux, Frédéric Blanc, Thierry Collette  Reconfigurable Computing 2003-WS-03
Cichon, Gordon
2003
MOUSE: A Shortcut from Matlab Source to SIMD DSP Assembly Code Gordon Cichon, Gerhard Fettweis Compilers, System Modeling, and Simulation 2003-WS-17
Collette, Thierry
2003
RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems Stéphane Chevobbe, Nicolas Ventroux, Frédéric Blanc, Thierry Collette  Reconfigurable Computing 2003-WS-03
Cotofana, Sorin Dan
2003
High-Level Energy Estimation for ARM-Based SOCs Dan Crisu, Sorin Dan Cotofana, Stamatis Vassiliadis, Petri Liuha  Compilers, System Modeling, and Simulation 2003-WS-18
Crisu, Dan
2003
High-Level Energy Estimation for ARM-Based SOCs Dan Crisu, Sorin Dan Cotofana, Stamatis Vassiliadis, Petri Liuha  Compilers, System Modeling, and Simulation 2003-WS-18
Demigny, Didier
2003
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon   Architectures and Implementation 2003-WS-14
Dimakopulos, Vassilios V.
2003
CoDeL: Automatically Synthesizing Network Interface Controllers Radhakrishnan Sivakumar, Vassilios V. Dimakopulos, Nikitas J. Dimopoulos Architectures and Implementation 2003-WS-09
Dimopoulos, Nikitas J.
2003
CoDeL: Automatically Synthesizing Network Interface Controllers Radhakrishnan Sivakumar, Vassilios V. Dimakopulos, Nikitas J. Dimopoulos Architectures and Implementation 2003-WS-09
Doerper, Malte
2003
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr   Architectures and Implementation 2003-WS-15
Erbas, Cagkan
2003
IDF Models for Trace Transformations: A Case Study in Computational Refinement Cagkan Erbas, Simon Polstra, Andy D. Pimentel Compilers, System Modeling, and Simulation 2003-WS-19
Fabiani, Erwan
2003
Intermediate Level Components for Reconfigurable Platforms Erwan Fabiani, Christophe Gouyen, Bernard Pottier Reconfigurable Computing 2003-WS-07
Fettweis, Gerhard
2003
MOUSE: A Shortcut from Matlab Source to SIMD DSP Assembly Code Gordon Cichon, Gerhard Fettweis Compilers, System Modeling, and Simulation 2003-WS-17
Gaydadjiev, Georgi N.
2003
The Molen Programming Paradigm Stamatis Vassiliadis, Georgi N. Gaydadjiev, Koen Bertels, Elena Moscu Panainte  Reconfigurable Computing 2003-WS-01
Gaydadjiev, Georgi N.
2003
Loading ρμ-Code: Design Considerations Georgi Kuzmanov, Georgi N. Gaydadjiev, Stamatis Vassiliadis Reconfigurable Computing 2003-WS-02
Gossens, Stefan
2003
An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs Ulrich Heinkel, Claus Mayer, Charles Webb, Hans Sahm, Werner Haas, Stefan Gossens   Architectures and Implementation 2003-WS-11
Gouyen, Christophe
2003
Intermediate Level Components for Reconfigurable Platforms Erwan Fabiani, Christophe Gouyen, Bernard Pottier Reconfigurable Computing 2003-WS-07
Gries, Ulrich
2003
A Cost-Efficient RISC Processor Platform for Real Time Audio Applications Jens Peter Wittenburg, Ulrich Schreiber, Ulrich Gries, Markus Schneider, Tim Niggemeier  Reconfigurable Computing 2003-WS-05
Guevorkian, David
2003
A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures David Guevorkian, Petri Liuha, Aki Launiainen, Ville Lappalainen  Architectures and Implementation 2003-WS-13
Haas, Werner
2003
An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs Ulrich Heinkel, Claus Mayer, Charles Webb, Hans Sahm, Werner Haas, Stefan Gossens   Architectures and Implementation 2003-WS-11
Hämäläinen, Timo D.
2003
Comparison of Data Dependence Analysis Tests Miia Viitanen, Timo D. Hämäläinen Compilers, System Modeling, and Simulation 2003-WS-16
Haubelt, Christian
2003
Basic OS Support for Distributed Reconfigurable Hardware Christian Haubelt, Dirk Koch, Jürgen Teich Reconfigurable Computing 2003-WS-04
Heinkel, Ulrich
2003
An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs Ulrich Heinkel, Claus Mayer, Charles Webb, Hans Sahm, Werner Haas, Stefan Gossens   Architectures and Implementation 2003-WS-11
Järvinen, Tuomas
2003
Register-Based Permutation Networks for Stride Permutations Tuomas Järvinen, Jarmo Takala Architectures and Implementation 2003-WS-12
Kempf, Torsten
2003
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr   Architectures and Implementation 2003-WS-15
Koch, Dirk
2003
Basic OS Support for Distributed Reconfigurable Hardware Christian Haubelt, Dirk Koch, Jürgen Teich Reconfigurable Computing 2003-WS-04
Kogel, Tim
2003
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr   Architectures and Implementation 2003-WS-15
Kuzmanov, Georgi
2003
Loading ρμ-Code: Design Considerations Georgi Kuzmanov, Georgi N. Gaydadjiev, Stamatis Vassiliadis Reconfigurable Computing 2003-WS-02
Langerwerf, Javier Martín
2003
Performance Estimation of Streaming Media Applications for Reconfigurable Platforms Carsten Reuter, Javier Martín Langerwerf, Hans-Joachim Stolberg, Peter Pirsch  Reconfigurable Computing 2003-WS-08
Lappalainen, Ville
2003
A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures David Guevorkian, Petri Liuha, Aki Launiainen, Ville Lappalainen  Architectures and Implementation 2003-WS-13
Launiainen, Aki
2003
A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures David Guevorkian, Petri Liuha, Aki Launiainen, Ville Lappalainen  Architectures and Implementation 2003-WS-13
Leupers, Rainer
2003
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr   Architectures and Implementation 2003-WS-15
Liuha, Petri
2003
A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures David Guevorkian, Petri Liuha, Aki Launiainen, Ville Lappalainen  Architectures and Implementation 2003-WS-13
Liuha, Petri
2003
High-Level Energy Estimation for ARM-Based SOCs Dan Crisu, Sorin Dan Cotofana, Stamatis Vassiliadis, Petri Liuha  Compilers, System Modeling, and Simulation 2003-WS-18
Llosa, Josep
2003
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero  Architectures and Implementation 2003-WS-10
Luk, Wayne
2003
Customising Processors: Design-Time and Run-Time Opportunities Wayne Luk  Reconfigurable Computing 2003-WS-06
Mayer, Claus
2003
An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs Ulrich Heinkel, Claus Mayer, Charles Webb, Hans Sahm, Werner Haas, Stefan Gossens   Architectures and Implementation 2003-WS-11
Meyr, Heinrich
2003
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr   Architectures and Implementation 2003-WS-15
Moscu Panainte, Elena
2003
The Molen Programming Paradigm Stamatis Vassiliadis, Georgi N. Gaydadjiev, Koen Bertels, Elena Moscu Panainte  Reconfigurable Computing 2003-WS-01
Niggemeier, Tim
2003
A Cost-Efficient RISC Processor Platform for Real Time Audio Applications Jens Peter Wittenburg, Ulrich Schreiber, Ulrich Gries, Markus Schneider, Tim Niggemeier  Reconfigurable Computing 2003-WS-05
Pericàs, Miquel
2003
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero  Architectures and Implementation 2003-WS-10
Pimentel, Andy D.
2003
IDF Models for Trace Transformations: A Case Study in Computational Refinement Cagkan Erbas, Simon Polstra, Andy D. Pimentel Compilers, System Modeling, and Simulation 2003-WS-19
Pirsch, Peter
2003
Performance Estimation of Streaming Media Applications for Reconfigurable Platforms Carsten Reuter, Javier Martín Langerwerf, Hans-Joachim Stolberg, Peter Pirsch  Reconfigurable Computing 2003-WS-08
Polstra, Simon
2003
IDF Models for Trace Transformations: A Case Study in Computational Refinement Cagkan Erbas, Simon Polstra, Andy D. Pimentel Compilers, System Modeling, and Simulation 2003-WS-19
Pottier, Bernard
2003
Intermediate Level Components for Reconfigurable Platforms Erwan Fabiani, Christophe Gouyen, Bernard Pottier Reconfigurable Computing 2003-WS-07
Reuter, Carsten
2003
Performance Estimation of Streaming Media Applications for Reconfigurable Platforms Carsten Reuter, Javier Martín Langerwerf, Hans-Joachim Stolberg, Peter Pirsch  Reconfigurable Computing 2003-WS-08
Robert, Michel
2003
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon   Architectures and Implementation 2003-WS-14
Sahm, Hans
2003
An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs Ulrich Heinkel, Claus Mayer, Charles Webb, Hans Sahm, Werner Haas, Stefan Gossens   Architectures and Implementation 2003-WS-11
Sassatelli, Gilles
2003
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon   Architectures and Implementation 2003-WS-14
Schneider, Markus
2003
A Cost-Efficient RISC Processor Platform for Real Time Audio Applications Jens Peter Wittenburg, Ulrich Schreiber, Ulrich Gries, Markus Schneider, Tim Niggemeier  Reconfigurable Computing 2003-WS-05
Schreiber, Ulrich
2003
A Cost-Efficient RISC Processor Platform for Real Time Audio Applications Jens Peter Wittenburg, Ulrich Schreiber, Ulrich Gries, Markus Schneider, Tim Niggemeier  Reconfigurable Computing 2003-WS-05
Sivakumar, Radhakrishnan
2003
CoDeL: Automatically Synthesizing Network Interface Controllers Radhakrishnan Sivakumar, Vassilios V. Dimakopulos, Nikitas J. Dimopoulos Architectures and Implementation 2003-WS-09
Stolberg, Hans-Joachim
2003
Performance Estimation of Streaming Media Applications for Reconfigurable Platforms Carsten Reuter, Javier Martín Langerwerf, Hans-Joachim Stolberg, Peter Pirsch  Reconfigurable Computing 2003-WS-08
Takala, Jarmo
2003
Register-Based Permutation Networks for Stride Permutations Tuomas Järvinen, Jarmo Takala Architectures and Implementation 2003-WS-12
Teich, Jürgen
2003
Basic OS Support for Distributed Reconfigurable Hardware Christian Haubelt, Dirk Koch, Jürgen Teich Reconfigurable Computing 2003-WS-04
Torres, Lionel
2003
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon   Architectures and Implementation 2003-WS-14
Valero, Mateo
2003
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero  Architectures and Implementation 2003-WS-10
Vassiliadis, Stamatis
2003
The Molen Programming Paradigm Stamatis Vassiliadis, Georgi N. Gaydadjiev, Koen Bertels, Elena Moscu Panainte  Reconfigurable Computing 2003-WS-01
Vassiliadis, Stamatis
2003
High-Level Energy Estimation for ARM-Based SOCs Dan Crisu, Sorin Dan Cotofana, Stamatis Vassiliadis, Petri Liuha  Compilers, System Modeling, and Simulation 2003-WS-18
Vassiliadis, Stamatis
2003
Loading ρμ-Code: Design Considerations Georgi Kuzmanov, Georgi N. Gaydadjiev, Stamatis Vassiliadis Reconfigurable Computing 2003-WS-02
Ventroux, Nicolas
2003
RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems Stéphane Chevobbe, Nicolas Ventroux, Frédéric Blanc, Thierry Collette  Reconfigurable Computing 2003-WS-03
Viitanen, Miia
2003
Comparison of Data Dependence Analysis Tests Miia Viitanen, Timo D. Hämäläinen Compilers, System Modeling, and Simulation 2003-WS-16
Webb, Charles
2003
An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs Ulrich Heinkel, Claus Mayer, Charles Webb, Hans Sahm, Werner Haas, Stefan Gossens   Architectures and Implementation 2003-WS-11
Wieferink, Andreas
2003
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr   Architectures and Implementation 2003-WS-15
Wittenburg, Jens Peter
2003
A Cost-Efficient RISC Processor Platform for Real Time Audio Applications Jens Peter Wittenburg, Ulrich Schreiber, Ulrich Gries, Markus Schneider, Tim Niggemeier  Reconfigurable Computing 2003-WS-05
Zalamea, Javier
2003
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero  Architectures and Implementation 2003-WS-10
Agarwal, Nainesh
2004
Using CoDeL to Rapidly Prototype Network Processsor Extensions Nainesh Agarwal, Nikitas J. Dimopoulos Architectures and Implementation 2004-WS-16
Alliot, Sylvain
2004
On the (Re-)Use of IP-Components in Re-configurable Platforms Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere Reconfigurable Computing 2004-WS-09
Antochi, Iosif
2004
Memory Bandwidth Requirements of Tile-Based Rendering Iosif Antochi, Ben Juurlink, Stamatis Vassiliadis, Petri Liuha  Architectures and Implementation 2004-WS-15
Ascheid, Gerd
2004
Early ISS Integration into Network-on-Chip Designs Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr   System Modeling  and Simulation 2004-WS-27
Ascheid, Gerd
2004
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun   System Modeling  and Simulation 2004-WS-29
Beck, Antonio Carlos S. 
2004
Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications Júlio C. B. Mattos, Antonio Carlos S. Beck, Luigi Carro, Flávio R. Wagner  Architectures and Implementation 2004-WS-13
Bertels, Koen
2004
Dynamic Hardware Reconfigurations: Performance Impact for MPEG2 Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis Reconfigurable Computing 2004-WS-11
Bhattacharyya, Shuvra S.
2004
DIF: An Interchange Format for Dataflow-Based Design Tools Chia-Jui Hsu, Fuat Keceli, Ming-Yung Ko, Shahrooz Shahparnia, Shuvra S. Bhattacharyya  System Modeling  and Simulation 2004-WS-25
Bhattacharyya, Shuvra S.
2004
Analysis of Dataflow Programs with Interval-Limited Data-Rates Jürgen Teich, Shuvra S. Bhattacharyya System Modeling  and Simulation 2004-WS-33
Blume, Holger
2004
Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets Holger Blume, Thorsten von Sydow, Tobias G. G. Noll System Modeling  and Simulation 2004-WS-31
Braun, Gunnar
2004
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun   System Modeling  and Simulation 2004-WS-29
Brockmeyer, Erik
2004
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis   System Modeling  and Simulation 2004-WS-36
Bronzel, Marcus
2004
Synchronous Transfer Architecture (STA) Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matúš, Marcus Bronzel, Gerhard Fettweis   Architectures and Implementation 2004-WS-17
Bronzel, Marcus
2004
Generated DSP Cores for Implementation of an OFDM Communication System Hendrik Seidel, Emil Matúš, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard Fettweis   Architectures and Implementation 2004-WS-18
Cambonie, Joël
2004
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators Joël Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, Samar Yazdani   Reconfigurable Computing 2004-WS-12
Cardoso, João M. P.
2004
Modeling Loop Unrolling: Approaches and Open Issues João M. P. Cardoso, Pedro C. Diniz Reconfigurable Computing 2004-WS-05
Cardoso, João M. P.
2004
Self-loop Pipelining and Reconfigurable Dataflow Arrays João M. P. Cardoso  Reconfigurable Computing 2004-WS-06
Carro, Luigi
2004
Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications Júlio C. B. Mattos, Antonio Carlos S. Beck, Luigi Carro, Flávio R. Wagner  Architectures and Implementation 2004-WS-13
Catthoor, Francky
2004
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis   System Modeling  and Simulation 2004-WS-36
Ceng, Jianjiang
2004
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun   System Modeling  and Simulation 2004-WS-29
Charot, François
2004
Architecture Exploration for 3G Telephony Applications Using a Hardware–Software Prototyping Platform François Charot, Madeleine Nyamsi, Patrice Quinton, Charles Wagner  Reconfigurable Computing 2004-WS-07
Cheung, Ray C. C.
2004
Customising Hardware Designs for Elliptic Curve Cryptography Nicolas Telle, Wayne Luk, Ray C. C. Cheung Reconfigurable Computing 2004-WS-10
Christiaens, Mark
2004
Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements Dirk Stroobandt, Hendrik Eeckhaut, Harald Devos, Mark Christiaens, Fabio Verdicchio, Peter Schelkens   Reconfigurable Computing 2004-WS-03
Cichon, Gordon
2004
Synchronous Transfer Architecture (STA) Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matúš, Marcus Bronzel, Gerhard Fettweis   Architectures and Implementation 2004-WS-17
Cichon, Gordon
2004
Generated DSP Cores for Implementation of an OFDM Communication System Hendrik Seidel, Emil Matúš, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard Fettweis   Architectures and Implementation 2004-WS-18
Cimpian, Ioan
2004
Communication Optimization in Compaan Process Networks Ioan Cimpian, Alexandru Turjan, Ed F. Deprettere, Erwin de Kock  System Modeling  and Simulation 2004-WS-32
Dasygenis, Minas
2004
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis   System Modeling  and Simulation 2004-WS-36
de Kock, Erwin
2004
Communication Optimization in Compaan Process Networks Ioan Cimpian, Alexandru Turjan, Ed F. Deprettere, Erwin de Kock  System Modeling  and Simulation 2004-WS-32
Deprettere, Ed F.
2004
On the (Re-)Use of IP-Components in Re-configurable Platforms Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere Reconfigurable Computing 2004-WS-09
Deprettere, Ed F.
2004
Communication Optimization in Compaan Process Networks Ioan Cimpian, Alexandru Turjan, Ed F. Deprettere, Erwin de Kock  System Modeling  and Simulation 2004-WS-32
Deprettere, Ed F.
2004
Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration Lauren?iu Nicolae, Ed F. Deprettere System Modeling  and Simulation 2004-WS-37
Devos, Harald
2004
Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements Dirk Stroobandt, Hendrik Eeckhaut, Harald Devos, Mark Christiaens, Fabio Verdicchio, Peter Schelkens   Reconfigurable Computing 2004-WS-03
Dimopoulos, Nikitas J.
2004
Using CoDeL to Rapidly Prototype Network Processsor Extensions Nainesh Agarwal, Nikitas J. Dimopoulos Architectures and Implementation 2004-WS-16
Diniz, Pedro C.
2004
Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques Pedro C. Diniz  Reconfigurable Computing 2004-WS-04
Diniz, Pedro C.
2004
Modeling Loop Unrolling: Approaches and Open Issues João M. P. Cardoso, Pedro C. Diniz Reconfigurable Computing 2004-WS-05
Doerper, Malte
2004
Early ISS Integration into Network-on-Chip Designs Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr   System Modeling  and Simulation 2004-WS-27
Durinck, Bart
2004
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis   System Modeling  and Simulation 2004-WS-36
Eeckhaut, Hendrik
2004
Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements Dirk Stroobandt, Hendrik Eeckhaut, Harald Devos, Mark Christiaens, Fabio Verdicchio, Peter Schelkens   Reconfigurable Computing 2004-WS-03
Feautrier, Paul
2004
Scalable and Modular Scheduling Paul Feautrier  System Modeling  and Simulation 2004-WS-26
Fettweis, Gerhard
2004
On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering Michael Hosemann, Gerhard Fettweis Architectures and Implementation 2004-WS-14
Fettweis, Gerhard
2004
Synchronous Transfer Architecture (STA) Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matúš, Marcus Bronzel, Gerhard Fettweis   Architectures and Implementation 2004-WS-17
Fettweis, Gerhard
2004
Generated DSP Cores for Implementation of an OFDM Communication System Hendrik Seidel, Emil Matúš, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard Fettweis   Architectures and Implementation 2004-WS-18
Fraboulet, Antoine
2004
Cycle Accurate Simulation Model Generation for SoC Prototyping Antoine Fraboulet, Tanguy Risset, Antoine Scherrer System Modeling  and Simulation 2004-WS-28
G. Noll, Tobias G.
2004
Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets Holger Blume, Thorsten von Sydow, Tobias G. G. Noll System Modeling  and Simulation 2004-WS-31
Galanis, Michalis D.
2004
A Novel Data-Path for Accelerating DSP Kernels Michalis D. Galanis, G. Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis  Architectures and Implementation 2004-WS-19
Gaydadjiev, Georgi N.
2004
The Virtex II Pro MOLEN Processor Georgi Kuzmanov, Georgi N. Gaydadjiev, Stamatis Vassiliadis Reconfigurable Computing 2004-WS-02
Glossner, John
2004
A Low-Power Multithreaded Processor for Baseband Communication Systems Michael Schulte, John Glossner, Suman Mamidi, Mayan Moudgill, Stamatis Vassiliadis  Architectures and Implementation 2004-WS-22
Goutis, Costas E.
2004
A Novel Data-Path for Accelerating DSP Kernels Michalis D. Galanis, G. Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis  Architectures and Implementation 2004-WS-19
Guérin, Sylvain
2004
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators Joël Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, Samar Yazdani   Reconfigurable Computing 2004-WS-12
Hämäläinen, Timo D.
2004
HIBI v.2 Communication Network for System-on-Chip Erno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen   Architectures and Implementation 2004-WS-24
Hämäläinen, Timo D.
2004
A Communication-Centric Design Flow for HIBI-Based SoCs Tero Kangas, Jouni Riihimäki, Erno Salminen, Vesa Lahtinen, Heikki Orsila, Kimmo Kuusilinna, Timo D. Hämäläinen   System Modeling  and Simulation 2004-WS-30
Hannig, Frank
2004
High-Speed Event-Driven RTL Compiled Simulation Alexey Kupriyanov, Frank Hannig, Jürgen Teich System Modeling  and Simulation 2004-WS-34
Hohenauer, Manuel
2004
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun   System Modeling  and Simulation 2004-WS-29
Hosemann, Michael
2004
On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering Michael Hosemann, Gerhard Fettweis Architectures and Implementation 2004-WS-14
Hsu, Chia-Jui
2004
DIF: An Interchange Format for Dataflow-Based Design Tools Chia-Jui Hsu, Fuat Keceli, Ming-Yung Ko, Shahrooz Shahparnia, Shuvra S. Bhattacharyya  System Modeling  and Simulation 2004-WS-25
Jesshope, Chris R.
2004
Scalable Instruction-Level Parallelism Chris R. Jesshope  Architectures and Implementation 2004-WS-21
Juurlink, Ben
2004
Memory Bandwidth Requirements of Tile-Based Rendering Iosif Antochi, Ben Juurlink, Stamatis Vassiliadis, Petri Liuha  Architectures and Implementation 2004-WS-15
Kangas, Tero
2004
HIBI v.2 Communication Network for System-on-Chip Erno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen   Architectures and Implementation 2004-WS-24
Kangas, Tero
2004
A Communication-Centric Design Flow for HIBI-Based SoCs Tero Kangas, Jouni Riihimäki, Erno Salminen, Vesa Lahtinen, Heikki Orsila, Kimmo Kuusilinna, Timo D. Hämäläinen   System Modeling  and Simulation 2004-WS-30
Keceli, Fuat
2004
DIF: An Interchange Format for Dataflow-Based Design Tools Chia-Jui Hsu, Fuat Keceli, Ming-Yung Ko, Shahrooz Shahparnia, Shuvra S. Bhattacharyya  System Modeling  and Simulation 2004-WS-25
Keryell, Ronan
2004
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators Joël Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, Samar Yazdani   Reconfigurable Computing 2004-WS-12
Ko, Ming-Yung
2004
DIF: An Interchange Format for Dataflow-Based Design Tools Chia-Jui Hsu, Fuat Keceli, Ming-Yung Ko, Shahrooz Shahparnia, Shuvra S. Bhattacharyya  System Modeling  and Simulation 2004-WS-25
Kogel, Tim
2004
Early ISS Integration into Network-on-Chip Designs Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr   System Modeling  and Simulation 2004-WS-27
Kupriyanov, Alexey
2004
High-Speed Event-Driven RTL Compiled Simulation Alexey Kupriyanov, Frank Hannig, Jürgen Teich System Modeling  and Simulation 2004-WS-34
Kuusilinna, Kimmo
2004
HIBI v.2 Communication Network for System-on-Chip Erno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen   Architectures and Implementation 2004-WS-24
Kuusilinna, Kimmo
2004
A Communication-Centric Design Flow for HIBI-Based SoCs Tero Kangas, Jouni Riihimäki, Erno Salminen, Vesa Lahtinen, Heikki Orsila, Kimmo Kuusilinna, Timo D. Hämäläinen   System Modeling  and Simulation 2004-WS-30
Kuzmanov, Georgi
2004
The Virtex II Pro MOLEN Processor Georgi Kuzmanov, Georgi N. Gaydadjiev, Stamatis Vassiliadis Reconfigurable Computing 2004-WS-02
Lagadec, Loïc
2004
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators Joël Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, Samar Yazdani   Reconfigurable Computing 2004-WS-12
Lahtinen, Vesa
2004
HIBI v.2 Communication Network for System-on-Chip Erno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen   Architectures and Implementation 2004-WS-24
Lahtinen, Vesa
2004
A Communication-Centric Design Flow for HIBI-Based SoCs Tero Kangas, Jouni Riihimäki, Erno Salminen, Vesa Lahtinen, Heikki Orsila, Kimmo Kuusilinna, Timo D. Hämäläinen   System Modeling  and Simulation 2004-WS-30
Lemaitre, Jérôme
2004
On the (Re-)Use of IP-Components in Re-configurable Platforms Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere Reconfigurable Computing 2004-WS-09
Leupers, Rainer
2004
Early ISS Integration into Network-on-Chip Designs Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr   System Modeling  and Simulation 2004-WS-27
Leupers, Rainer
2004
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun   System Modeling  and Simulation 2004-WS-29
Liuha, Petri
2004
Memory Bandwidth Requirements of Tile-Based Rendering Iosif Antochi, Ben Juurlink, Stamatis Vassiliadis, Petri Liuha  Architectures and Implementation 2004-WS-15
Luk, Wayne
2004
Customising Hardware Designs for Elliptic Curve Cryptography Nicolas Telle, Wayne Luk, Ray C. C. Cheung Reconfigurable Computing 2004-WS-10
Mamidi, Suman
2004
A Low-Power Multithreaded Processor for Baseband Communication Systems Michael Schulte, John Glossner, Suman Mamidi, Mayan Moudgill, Stamatis Vassiliadis  Architectures and Implementation 2004-WS-22
Mattos, Júlio C. B.
2004
Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications Júlio C. B. Mattos, Antonio Carlos S. Beck, Luigi Carro, Flávio R. Wagner  Architectures and Implementation 2004-WS-13
Matúš, Emil
2004
Synchronous Transfer Architecture (STA) Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matúš, Marcus Bronzel, Gerhard Fettweis   Architectures and Implementation 2004-WS-17
Matúš, Emil
2004
Generated DSP Cores for Implementation of an OFDM Communication System Hendrik Seidel, Emil Matúš, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard Fettweis   Architectures and Implementation 2004-WS-18
McAllister, John
2004
Embedded Context Aware Hardware Component Generation for Dataflow System Exploration John McAllister, Roger Woods, Richard Walke Reconfigurable Computing 2004-WS-08
Meyr, Heinrich
2004
Early ISS Integration into Network-on-Chip Designs Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr   System Modeling  and Simulation 2004-WS-27
Meyr, Heinrich
2004
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun   System Modeling  and Simulation 2004-WS-29
Moscu Panainte, Elena
2004
Dynamic Hardware Reconfigurations: Performance Impact for MPEG2 Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis Reconfigurable Computing 2004-WS-11
Moudgill, Mayan
2004
A Low-Power Multithreaded Processor for Baseband Communication Systems Michael Schulte, John Glossner, Suman Mamidi, Mayan Moudgill, Stamatis Vassiliadis  Architectures and Implementation 2004-WS-22
Nicolae, Lauren?iu
2004
Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration Lauren?iu Nicolae, Ed F. Deprettere System Modeling  and Simulation 2004-WS-37
Nyamsi, Madeleine
2004
Architecture Exploration for 3G Telephony Applications Using a Hardware–Software Prototyping Platform François Charot, Madeleine Nyamsi, Patrice Quinton, Charles Wagner  Reconfigurable Computing 2004-WS-07
Orsila, Heikki
2004
A Communication-Centric Design Flow for HIBI-Based SoCs Tero Kangas, Jouni Riihimäki, Erno Salminen, Vesa Lahtinen, Heikki Orsila, Kimmo Kuusilinna, Timo D. Hämäläinen   System Modeling  and Simulation 2004-WS-30
Pimentel, Andy D.
2004
A High-Level Programming Paradigm for SystemC Mark Thompson, Andy D. Pimentel System Modeling  and Simulation 2004-WS-35
Pottier, Bernard
2004
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators Joël Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, Samar Yazdani   Reconfigurable Computing 2004-WS-12
Punkka, Konsta
2004
Scalable FFT Processors and Pipelined Butterfly Units Jarmo Takala, Konsta Punkka Architectures and Implementation 2004-WS-20
Quinton, Patrice
2004
Architecture Exploration for 3G Telephony Applications Using a Hardware–Software Prototyping Platform François Charot, Madeleine Nyamsi, Patrice Quinton, Charles Wagner  Reconfigurable Computing 2004-WS-07
Riihimäki, Jouni
2004
HIBI v.2 Communication Network for System-on-Chip Erno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen   Architectures and Implementation 2004-WS-24
Riihimäki, Jouni
2004
A Communication-Centric Design Flow for HIBI-Based SoCs Tero Kangas, Jouni Riihimäki, Erno Salminen, Vesa Lahtinen, Heikki Orsila, Kimmo Kuusilinna, Timo D. Hämäläinen   System Modeling  and Simulation 2004-WS-30
Risset, Tanguy
2004
Cycle Accurate Simulation Model Generation for SoC Prototyping Antoine Fraboulet, Tanguy Risset, Antoine Scherrer System Modeling  and Simulation 2004-WS-28
Robelly, Pablo
2004
Synchronous Transfer Architecture (STA) Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matúš, Marcus Bronzel, Gerhard Fettweis   Architectures and Implementation 2004-WS-17
Robelly, Pablo
2004
Generated DSP Cores for Implementation of an OFDM Communication System Hendrik Seidel, Emil Matúš, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard Fettweis   Architectures and Implementation 2004-WS-18
Salamí, Esther
2004
Initial Evaluation of Multimedia Extensions on VLIW Architectures Esther Salamí, Mateo Valero Architectures and Implementation 2004-WS-23
Salminen, Erno
2004
HIBI v.2 Communication Network for System-on-Chip Erno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen   Architectures and Implementation 2004-WS-24
Salminen, Erno
2004
A Communication-Centric Design Flow for HIBI-Based SoCs Tero Kangas, Jouni Riihimäki, Erno Salminen, Vesa Lahtinen, Heikki Orsila, Kimmo Kuusilinna, Timo D. Hämäläinen   System Modeling  and Simulation 2004-WS-30
Schelkens, Peter
2004
Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements Dirk Stroobandt, Hendrik Eeckhaut, Harald Devos, Mark Christiaens, Fabio Verdicchio, Peter Schelkens   Reconfigurable Computing 2004-WS-03
Scherrer, Antoine
2004
Cycle Accurate Simulation Model Generation for SoC Prototyping Antoine Fraboulet, Tanguy Risset, Antoine Scherrer System Modeling  and Simulation 2004-WS-28
Schulte, Michael
2004
A Low-Power Multithreaded Processor for Baseband Communication Systems Michael Schulte, John Glossner, Suman Mamidi, Mayan Moudgill, Stamatis Vassiliadis  Architectures and Implementation 2004-WS-22
Seidel, Hendrik
2004
Synchronous Transfer Architecture (STA) Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matúš, Marcus Bronzel, Gerhard Fettweis   Architectures and Implementation 2004-WS-17
Seidel, Hendrik
2004
Generated DSP Cores for Implementation of an OFDM Communication System Hendrik Seidel, Emil Matúš, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard Fettweis   Architectures and Implementation 2004-WS-18
Sentieys, Olivier
2004
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators Joël Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, Samar Yazdani   Reconfigurable Computing 2004-WS-12
Shahparnia, Shahrooz
2004
DIF: An Interchange Format for Dataflow-Based Design Tools Chia-Jui Hsu, Fuat Keceli, Ming-Yung Ko, Shahrooz Shahparnia, Shuvra S. Bhattacharyya  System Modeling  and Simulation 2004-WS-25
Sheng, Weihua
2004
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun   System Modeling  and Simulation 2004-WS-29
Soudris, Dimitrios
2004
A Novel Data-Path for Accelerating DSP Kernels Michalis D. Galanis, G. Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis  Architectures and Implementation 2004-WS-19
Soudris, Dimitrios
2004
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis   System Modeling  and Simulation 2004-WS-36
Stroobandt, Dirk
2004
Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements Dirk Stroobandt, Hendrik Eeckhaut, Harald Devos, Mark Christiaens, Fabio Verdicchio, Peter Schelkens   Reconfigurable Computing 2004-WS-03
Takala, Jarmo
2004
Scalable FFT Processors and Pipelined Butterfly Units Jarmo Takala, Konsta Punkka Architectures and Implementation 2004-WS-20
Teich, Jürgen
2004
Analysis of Dataflow Programs with Interval-Limited Data-Rates Jürgen Teich, Shuvra S. Bhattacharyya System Modeling  and Simulation 2004-WS-33
Teich, Jürgen
2004
High-Speed Event-Driven RTL Compiled Simulation Alexey Kupriyanov, Frank Hannig, Jürgen Teich System Modeling  and Simulation 2004-WS-34
Telle, Nicolas
2004
Customising Hardware Designs for Elliptic Curve Cryptography Nicolas Telle, Wayne Luk, Ray C. C. Cheung Reconfigurable Computing 2004-WS-10
Thanailakis, Antonios
2004
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis   System Modeling  and Simulation 2004-WS-36
Theodoridis, G.
2004
A Novel Data-Path for Accelerating DSP Kernels Michalis D. Galanis, G. Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis  Architectures and Implementation 2004-WS-19
Thompson, Mark
2004
A High-Level Programming Paradigm for SystemC Mark Thompson, Andy D. Pimentel System Modeling  and Simulation 2004-WS-35
Tragoudas, Spyros
2004
A Novel Data-Path for Accelerating DSP Kernels Michalis D. Galanis, G. Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis  Architectures and Implementation 2004-WS-19
Turjan, Alexandru
2004
Communication Optimization in Compaan Process Networks Ioan Cimpian, Alexandru Turjan, Ed F. Deprettere, Erwin de Kock  System Modeling  and Simulation 2004-WS-32
Valero, Mateo
2004
Initial Evaluation of Multimedia Extensions on VLIW Architectures Esther Salamí, Mateo Valero Architectures and Implementation 2004-WS-23
Vassiliadis, Stamatis
2004
The Virtex II Pro MOLEN Processor Georgi Kuzmanov, Georgi N. Gaydadjiev, Stamatis Vassiliadis Reconfigurable Computing 2004-WS-02
Vassiliadis, Stamatis
2004
Dynamic Hardware Reconfigurations: Performance Impact for MPEG2 Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis Reconfigurable Computing 2004-WS-11
Vassiliadis, Stamatis
2004
Memory Bandwidth Requirements of Tile-Based Rendering Iosif Antochi, Ben Juurlink, Stamatis Vassiliadis, Petri Liuha  Architectures and Implementation 2004-WS-15
Vassiliadis, Stamatis
2004
A Low-Power Multithreaded Processor for Baseband Communication Systems Michael Schulte, John Glossner, Suman Mamidi, Mayan Moudgill, Stamatis Vassiliadis  Architectures and Implementation 2004-WS-22
Verdicchio, Fabio
2004
Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements Dirk Stroobandt, Hendrik Eeckhaut, Harald Devos, Mark Christiaens, Fabio Verdicchio, Peter Schelkens   Reconfigurable Computing 2004-WS-03
Vissers, Kees
2004
Programming Extremely Flexible Platforms -- Keynote Speech Kees Vissers  SAMOS IV - Keynote 2004-WS-01
von Sydow, Thorsten
2004
Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets Holger Blume, Thorsten von Sydow, Tobias G. G. Noll System Modeling  and Simulation 2004-WS-31
Wagner, Charles
2004
Architecture Exploration for 3G Telephony Applications Using a Hardware–Software Prototyping Platform François Charot, Madeleine Nyamsi, Patrice Quinton, Charles Wagner  Reconfigurable Computing 2004-WS-07
Wagner, Flávio R.
2004
Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications Júlio C. B. Mattos, Antonio Carlos S. Beck, Luigi Carro, Flávio R. Wagner  Architectures and Implementation 2004-WS-13
Walke, Richard
2004
Embedded Context Aware Hardware Component Generation for Dataflow System Exploration John McAllister, Roger Woods, Richard Walke Reconfigurable Computing 2004-WS-08
Weber, Bernt
2004
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators Joël Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, Samar Yazdani   Reconfigurable Computing 2004-WS-12
Wieferink, Andreas
2004
Early ISS Integration into Network-on-Chip Designs Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr   System Modeling  and Simulation 2004-WS-27
Woods, Roger
2004
Embedded Context Aware Hardware Component Generation for Dataflow System Exploration John McAllister, Roger Woods, Richard Walke Reconfigurable Computing 2004-WS-08
Yazdani, Samar
2004
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators Joël Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, Samar Yazdani   Reconfigurable Computing 2004-WS-12
Abdelli, N.
2005
DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context P. Bomel, N. Abdelli, E. Martin, A.-M. Fouilliart, E. Boutillon, P. Kajfasz   System Level Design, Modeling and Simulation 2005-WS-45
Becker, Daniel
2005
Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll  System Level Design, Modeling and Simulation 2005-WS-40
Beemster, Marcel
2005
Generating Stream Based Code from Plain C Marcel Beemster, Hans van Someren, Liam Fitzpatrick, Ruben van Royen  Processor Architectures, Design and Simulation 2005-WS-25
Bertels, Koen
2005
Interprocedural Optimization for Dynamic Hardware Configurations Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis Reconfigurable System Design and Implementations 2005-WS-02
Blume, Holger
2005
Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll  System Level Design, Modeling and Simulation 2005-WS-40
Bomel, P.
2005
DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context P. Bomel, N. Abdelli, E. Martin, A.-M. Fouilliart, E. Boutillon, P. Kajfasz   System Level Design, Modeling and Simulation 2005-WS-45
Bos, Herbert
2005
FPL-3E: Towards Language Support for Reconfigurable Packet Processing Mihai Lucian Cristea, Claudiu Zissulescu, Ed F. Deprettere, Herbert Bos  Reconfigurable System Design and Implementations 2005-WS-10
Bossuet, Lilian
2005
Configurable Computing for High-Security/High-Performance Ambient Systems Guy Gogniat, Wayne Burleson, Lilian Bossuet Reconfigurable System Design and Implementations 2005-WS-09
Boutillon, E.
2005
DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context P. Bomel, N. Abdelli, E. Martin, A.-M. Fouilliart, E. Boutillon, P. Kajfasz   System Level Design, Modeling and Simulation 2005-WS-45
Burleson, Wayne
2005
Configurable Computing for High-Security/High-Performance Ambient Systems Guy Gogniat, Wayne Burleson, Lilian Bossuet Reconfigurable System Design and Implementations 2005-WS-09
Calderón, Humberto
2005
Reconfigurable Multiple Operation Array Humberto Calderón, Stamatis Vassiliadis Reconfigurable System Design and Implementations 2005-WS-04
Cardoso, João M. P.
2005
Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping Ricardo Ferreira, João M. P. Cardoso, Andre Toledo, Horácio C. Neto  Reconfigurable System Design and Implementations 2005-WS-06
Carlomagno Filho, José O.
2005
Automatic ADL-Based Assembler Generation for ASIP Programming Support Leonardo Taglietti, José O. Carlomagno Filho, Daniel C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos  Processor Architectures, Design and Simulation 2005-WS-28
Casarotto, Daniel C.
2005
Automatic ADL-Based Assembler Generation for ASIP Programming Support Leonardo Taglietti, José O. Carlomagno Filho, Daniel C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos  Processor Architectures, Design and Simulation 2005-WS-28
Catthoor, Francky
2005
Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications Marijn Temmerman, Edgar G. Daylight, Francky Catthoor, Serge Demeyer, Tom Dhaene  System Level Design, Modeling and Simulation 2005-WS-47
Chang, Hoseok
2005
Compressed Swapping for NAND Flash Memory Based Embedded Systems Sangduck Park, Hyunjin Lim, Hoseok Chang, Wonyong Sung  Architectures and Implementations 2005-WS-34
Cho, Yookun
2005
Fast Real-Time Job Selection with Resource Constraints Under Earliest Deadline First Sangchul Han, Moonju Park, Yookun Cho Processor Architectures, Design and Simulation 2005-WS-26
Chung, Sung Woo
2005
First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption Cheol Hong Kim, Sunghoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon  Processor Architectures, Design and Simulation 2005-WS-12
Cilio, Andrea
2005
Hardware Cost Estimation for Application-Specific Processor Design Teemu Pitkänen, Tommi Rantanen, Andrea Cilio, Jarmo Takala  Processor Architectures, Design and Simulation 2005-WS-23
Cristea, Mihai Lucian
2005
FPL-3E: Towards Language Support for Reconfigurable Packet Processing Mihai Lucian Cristea, Claudiu Zissulescu, Ed F. Deprettere, Herbert Bos  Reconfigurable System Design and Implementations 2005-WS-10
Daylight, Edgar G.
2005
Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications Marijn Temmerman, Edgar G. Daylight, Francky Catthoor, Serge Demeyer, Tom Dhaene  System Level Design, Modeling and Simulation 2005-WS-47
De Bosschere, Koen
2005
Offline Phase Analysis and Optimization for Multi-configuration Processors Frederik Vandeputte, Lieven Eeckhout, Koen De Bosschere Processor Architectures, Design and Simulation 2005-WS-22
Demeyer, Serge
2005
Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications Marijn Temmerman, Edgar G. Daylight, Francky Catthoor, Serge Demeyer, Tom Dhaene  System Level Design, Modeling and Simulation 2005-WS-47
Deprettere, Ed F.
2005
FPL-3E: Towards Language Support for Reconfigurable Packet Processing Mihai Lucian Cristea, Claudiu Zissulescu, Ed F. Deprettere, Herbert Bos  Reconfigurable System Design and Implementations 2005-WS-10
Dhaene, Tom
2005
Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications Marijn Temmerman, Edgar G. Daylight, Francky Catthoor, Serge Demeyer, Tom Dhaene  System Level Design, Modeling and Simulation 2005-WS-47
Dorward, Sean
2005
Sandbridge Software Tools John Glossner, Sean Dorward, Sanjay Jinturkar, Mayan Moudgill, Erdem Hokenek, Michael Schulte, Stamatis Vassiliadis   Processor Architectures, Design and Simulation 2005-WS-29
dos Santos, Luiz C. V.
2005
Automatic ADL-Based Assembler Generation for ASIP Programming Support Leonardo Taglietti, José O. Carlomagno Filho, Daniel C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos  Processor Architectures, Design and Simulation 2005-WS-28
Dutta, Hritam
2005
Automatic FIR Filter Generation for FPGAs Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich  Reconfigurable System Design and Implementations 2005-WS-07
Eeckhout, Lieven
2005
Offline Phase Analysis and Optimization for Multi-configuration Processors Frederik Vandeputte, Lieven Eeckhout, Koen De Bosschere Processor Architectures, Design and Simulation 2005-WS-22
Eilers, Stefan
2005
Mixed Virtual/Real Prototypes for Incremental System Design – A Proof of Concept Stefan Eilers, C. Müller-Schloer System Level Design, Modeling and Simulation 2005-WS-49
Evripidou, Paraskevas
2005
DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor Kyriakos Stavrou, Paraskevas Evripidou, Pedro Trancoso Architectures and Implementations 2005-WS-39
Farfeleder, Stefan
2005
Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures Stefan Farfeleder, Andreas Krall, Nigel Horspool Processor Architectures, Design and Simulation 2005-WS-24
Ferreira, Ricardo
2005
Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping Ricardo Ferreira, João M. P. Cardoso, Andre Toledo, Horácio C. Neto  Reconfigurable System Design and Implementations 2005-WS-06
Fettweis, Gerhard
2005
Two-Dimensional Fast Cosine Transform for Vector-STA Architectures J. P. Robelly, A. Lehmann, Gerhard Fettweis Reconfigurable System Design and Implementations 2005-WS-08
Fischaber, Scott
2005
Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms John McAllister, Roger Woods, D. Reilly, Scott Fischaber, R. Hasson  System Level Design, Modeling and Simulation 2005-WS-44
Fitzpatrick, Liam
2005
Generating Stream Based Code from Plain C Marcel Beemster, Hans van Someren, Liam Fitzpatrick, Ruben van Royen  Processor Architectures, Design and Simulation 2005-WS-25
Fong, Anthony S.
2005
A Novel JAVA Processor for Embedded Devices Yiyu Tan, Chihang Yau, Kaiman Lo, Paklun Mok, Anthony S. Fong  Processor Architectures, Design and Simulation 2005-WS-13
Fouilliart, A.-M.
2005
DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context P. Bomel, N. Abdelli, E. Martin, A.-M. Fouilliart, E. Boutillon, P. Kajfasz   System Level Design, Modeling and Simulation 2005-WS-45
Furtado, Olinto J. V.
2005
Automatic ADL-Based Assembler Generation for ASIP Programming Support Leonardo Taglietti, José O. Carlomagno Filho, Daniel C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos  Processor Architectures, Design and Simulation 2005-WS-28
Gao, Fei
2005
Exploiting Intra-function Correlation with the Global History Stack Fei Gao, Suleyman Sair Processor Architectures, Design and Simulation 2005-WS-19
Gaydadjiev, Georgi N.
2005
Flux Caches: What Are They and Are They Useful? Georgi N. Gaydadjiev, Stamatis Vassiliadis Processor Architectures, Design and Simulation 2005-WS-11
Glesner, M.
2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques M. Glesner, H. Hinkelmann, T. Hollstein, L. S. Indrusiak, T. Murgan, A.M. Obeid, M. Petrov, T. Pionteck, P. Zipf  Reconfigurable System Design and Implementations 2005-WS-03
Glossner, John
2005
CORDIC-Augmented Sandbridge Processor for Channel Equalization Mihai Sima, John Glossner, Daniel Iancu, Hua Ye, Andrei Iancu, A. Joseph Hoane   Processor Architectures, Design and Simulation 2005-WS-17
Glossner, John
2005
Sandbridge Software Tools John Glossner, Sean Dorward, Sanjay Jinturkar, Mayan Moudgill, Erdem Hokenek, Michael Schulte, Stamatis Vassiliadis   Processor Architectures, Design and Simulation 2005-WS-29
Gogniat, Guy
2005
Configurable Computing for High-Security/High-Performance Ambient Systems Guy Gogniat, Wayne Burleson, Lilian Bossuet Reconfigurable System Design and Implementations 2005-WS-09
Goksu, Huseyin
2005
Application of Very Fast Simulated Reannealing (VFSR) to Low Power Design Ali Manzak, Huseyin Goksu Architectures and Implementations 2005-WS-33
Goudarzi, Maziar
2005
The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models Maziar Goudarzi, Shaahin Hessabi System Level Design, Modeling and Simulation 2005-WS-42
Gries, Matthias
2005
SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC Sören Sonntag, Matthias Gries, Christian Sauer System Level Design, Modeling and Simulation 2005-WS-46
Guevorkian, David
2005
A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms David Guevorkian, Petri Liuha, Aki Launiainen, Konsta Punkka, Ville Lappalainen  Architectures and Implementations 2005-WS-35
Hämäläinen, Timo D.
2005
Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context Erno Salminen, Tero Kangas, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, Timo D. Hämäläinen   Architectures and Implementations 2005-WS-38
Hämäläinen, Timo D.
2005
High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks Mauri Kuorilehto, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen  System Level Design, Modeling and Simulation 2005-WS-41
Hämäläinen, Timo D.
2005
Design and Implementation of a WLAN Terminal Using UML 2.0 Based Design Flow Petri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen System Level Design, Modeling and Simulation 2005-WS-43
Han, Sangchul
2005
Fast Real-Time Job Selection with Resource Constraints Under Earliest Deadline First Sangchul Han, Moonju Park, Yookun Cho Processor Architectures, Design and Simulation 2005-WS-26
Hannig, Frank
2005
Automatic FIR Filter Generation for FPGAs Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich  Reconfigurable System Design and Implementations 2005-WS-07
Hännikäinen, Marko
2005
High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks Mauri Kuorilehto, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen  System Level Design, Modeling and Simulation 2005-WS-41
Hännikäinen, Marko
2005
Design and Implementation of a WLAN Terminal Using UML 2.0 Based Design Flow Petri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen System Level Design, Modeling and Simulation 2005-WS-43
Hasson, R.
2005
Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms John McAllister, Roger Woods, D. Reilly, Scott Fischaber, R. Hasson  System Level Design, Modeling and Simulation 2005-WS-44
He, Lei
2005
Micro-architecture Performance Estimation by Formula Lucanus J. Simonson, Lei He Processor Architectures, Design and Simulation 2005-WS-21
Hessabi, Shaahin
2005
The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models Maziar Goudarzi, Shaahin Hessabi System Level Design, Modeling and Simulation 2005-WS-42
Hinkelmann, H.
2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques M. Glesner, H. Hinkelmann, T. Hollstein, L. S. Indrusiak, T. Murgan, A.M. Obeid, M. Petrov, T. Pionteck, P. Zipf  Reconfigurable System Design and Implementations 2005-WS-03
Hoane, A. Joseph
2005
CORDIC-Augmented Sandbridge Processor for Channel Equalization Mihai Sima, John Glossner, Daniel Iancu, Hua Ye, Andrei Iancu, A. Joseph Hoane   Processor Architectures, Design and Simulation 2005-WS-17
Hokenek, Erdem
2005
Sandbridge Software Tools John Glossner, Sean Dorward, Sanjay Jinturkar, Mayan Moudgill, Erdem Hokenek, Michael Schulte, Stamatis Vassiliadis   Processor Architectures, Design and Simulation 2005-WS-29
Hollstein, T.
2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques M. Glesner, H. Hinkelmann, T. Hollstein, L. S. Indrusiak, T. Murgan, A.M. Obeid, M. Petrov, T. Pionteck, P. Zipf  Reconfigurable System Design and Implementations 2005-WS-03
Hong, Xianlong
2005
A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan  Architectures and Implementations 2005-WS-37
Horspool, Nigel
2005
Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures Stefan Farfeleder, Andreas Krall, Nigel Horspool Processor Architectures, Design and Simulation 2005-WS-24
Hu, Xiaodong
2005
A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan  Architectures and Implementations 2005-WS-37
Hu, Yu
2005
A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan  Architectures and Implementations 2005-WS-37
Iancu, Andrei
2005
CORDIC-Augmented Sandbridge Processor for Channel Equalization Mihai Sima, John Glossner, Daniel Iancu, Hua Ye, Andrei Iancu, A. Joseph Hoane   Processor Architectures, Design and Simulation 2005-WS-17
Iancu, Daniel
2005
CORDIC-Augmented Sandbridge Processor for Channel Equalization Mihai Sima, John Glossner, Daniel Iancu, Hua Ye, Andrei Iancu, A. Joseph Hoane   Processor Architectures, Design and Simulation 2005-WS-17
Iannucci, Bob
2005
Platform Thinking in Embedded Systems Bob Iannucci  SAMOS V - Keynote 2005-WS-01
Indrusiak, L. S.
2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques M. Glesner, H. Hinkelmann, T. Hollstein, L. S. Indrusiak, T. Murgan, A.M. Obeid, M. Petrov, T. Pionteck, P. Zipf  Reconfigurable System Design and Implementations 2005-WS-03
Isoaho, Jouni
2005
Tuning a Protocol Processor Architecture Towards DSP Operations Jani Paakkulainen, Seppo Virtanen, Jouni Isoaho Processor Architectures, Design and Simulation 2005-WS-15
Jhang, Sung Tae
2005
Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic Sunghoon Shim, Jong Wook Kwak, Cheol Hong Kim, Sung Tae Jhang, Chu Shik Jhon  Processor Architectures, Design and Simulation 2005-WS-18
Jhon, Chu Shik
2005
First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption Cheol Hong Kim, Sunghoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon  Processor Architectures, Design and Simulation 2005-WS-12
Jhon, Chu Shik
2005
Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic Sunghoon Shim, Jong Wook Kwak, Cheol Hong Kim, Sung Tae Jhang, Chu Shik Jhon  Processor Architectures, Design and Simulation 2005-WS-18
Jing, Tong
2005
A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan  Architectures and Implementations 2005-WS-37
Jinturkar, Sanjay
2005
Sandbridge Software Tools John Glossner, Sean Dorward, Sanjay Jinturkar, Mayan Moudgill, Erdem Hokenek, Michael Schulte, Stamatis Vassiliadis   Processor Architectures, Design and Simulation 2005-WS-29
Jyrkkä, Kari
2005
Observations on Power-Efficiency Trends in Mobile Communication Devices Olli Silven, Kari Jyrkkä Processor Architectures, Design and Simulation 2005-WS-16
Kajfasz, P.
2005
DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context P. Bomel, N. Abdelli, E. Martin, A.-M. Fouilliart, E. Boutillon, P. Kajfasz   System Level Design, Modeling and Simulation 2005-WS-45
Kangas, Tero
2005
Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context Erno Salminen, Tero Kangas, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, Timo D. Hämäläinen   Architectures and Implementations 2005-WS-38
Kim, Cheol Hong
2005
First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption Cheol Hong Kim, Sunghoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon  Processor Architectures, Design and Simulation 2005-WS-12
Kim, Cheol Hong
2005
Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic Sunghoon Shim, Jong Wook Kwak, Cheol Hong Kim, Sung Tae Jhang, Chu Shik Jhon  Processor Architectures, Design and Simulation 2005-WS-18
Kim, JunSeong
2005
Real-Time Stereo Vision on a Reconfigurable System SungHwan Lee, Jongsu Yi, JunSeong Kim Architectures and Implementations 2005-WS-32
Kim, Sunil
2005
Pattern Matching Acceleration for Network Intrusion Detection Systems Sunil Kim  Architectures and Implementations 2005-WS-31
Kohvakka, Mikko
2005
High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks Mauri Kuorilehto, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen  System Level Design, Modeling and Simulation 2005-WS-41
Krall, Andreas
2005
Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures Stefan Farfeleder, Andreas Krall, Nigel Horspool Processor Architectures, Design and Simulation 2005-WS-24
Kukkala, Petri
2005
Design and Implementation of a WLAN Terminal Using UML 2.0 Based Design Flow Petri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen System Level Design, Modeling and Simulation 2005-WS-43
Kuorilehto, Mauri
2005
High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks Mauri Kuorilehto, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen  System Level Design, Modeling and Simulation 2005-WS-41
Kurdahi, Fadi J.
2005
A Scalable Embedded JPEG2000 Architecture Chunhui Zhang, Yun Long, Fadi J. Kurdahi Architectures and Implementations 2005-WS-36
Kuusilinna, Kimmo
2005
Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context Erno Salminen, Tero Kangas, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, Timo D. Hämäläinen   Architectures and Implementations 2005-WS-38
Kwak, Jong Wook
2005
First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption Cheol Hong Kim, Sunghoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon  Processor Architectures, Design and Simulation 2005-WS-12
Kwak, Jong Wook
2005
Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic Sunghoon Shim, Jong Wook Kwak, Cheol Hong Kim, Sung Tae Jhang, Chu Shik Jhon  Processor Architectures, Design and Simulation 2005-WS-18
Lahtinen, Vesa
2005
Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context Erno Salminen, Tero Kangas, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, Timo D. Hämäläinen   Architectures and Implementations 2005-WS-38
Langerwerf, Javier Martín
2005
RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration Guillermo Payá Vayá, Javier Martín Langerwerf, Peter Pirsch Reconfigurable System Design and Implementations 2005-WS-05
Lappalainen, Ville
2005
A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms David Guevorkian, Petri Liuha, Aki Launiainen, Konsta Punkka, Ville Lappalainen  Architectures and Implementations 2005-WS-35
Launiainen, Aki
2005
A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms David Guevorkian, Petri Liuha, Aki Launiainen, Konsta Punkka, Ville Lappalainen  Architectures and Implementations 2005-WS-35
Lee, SungHwan
2005
Real-Time Stereo Vision on a Reconfigurable System SungHwan Lee, Jongsu Yi, JunSeong Kim Architectures and Implementations 2005-WS-32
Lehmann, A.
2005
Two-Dimensional Fast Cosine Transform for Vector-STA Architectures J. P. Robelly, A. Lehmann, Gerhard Fettweis Reconfigurable System Design and Implementations 2005-WS-08
Li, Zeng-Zhi
2005
A Programming Model for an Embedded Media Processing Architecture Dan Zhang, Zeng-Zhi Li, Hong Song, Long Liu  Processor Architectures, Design and Simulation 2005-WS-27
Lim, Hyunjin
2005
Compressed Swapping for NAND Flash Memory Based Embedded Systems Sangduck Park, Hyunjin Lim, Hoseok Chang, Wonyong Sung  Architectures and Implementations 2005-WS-34
Liu, Long
2005
A Programming Model for an Embedded Media Processing Architecture Dan Zhang, Zeng-Zhi Li, Hong Song, Long Liu  Processor Architectures, Design and Simulation 2005-WS-27
Liuha, Petri
2005
A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms David Guevorkian, Petri Liuha, Aki Launiainen, Konsta Punkka, Ville Lappalainen  Architectures and Implementations 2005-WS-35
Lo, Kaiman
2005
A Novel JAVA Processor for Embedded Devices Yiyu Tan, Chihang Yau, Kaiman Lo, Paklun Mok, Anthony S. Fong  Processor Architectures, Design and Simulation 2005-WS-13
Long, Yun
2005
A Scalable Embedded JPEG2000 Architecture Chunhui Zhang, Yun Long, Fadi J. Kurdahi Architectures and Implementations 2005-WS-36
Manzak, Ali
2005
Application of Very Fast Simulated Reannealing (VFSR) to Low Power Design Ali Manzak, Huseyin Goksu Architectures and Implementations 2005-WS-33
Marchand, Philippe
2005
A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems Philippe Marchand, Purnendu Sinha Architectures and Implementations 2005-WS-30
Martin, E.
2005
DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context P. Bomel, N. Abdelli, E. Martin, A.-M. Fouilliart, E. Boutillon, P. Kajfasz   System Level Design, Modeling and Simulation 2005-WS-45
McAllister, John
2005
Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms John McAllister, Roger Woods, D. Reilly, Scott Fischaber, R. Hasson  System Level Design, Modeling and Simulation 2005-WS-44
Mok, Paklun
2005
A Novel JAVA Processor for Embedded Devices Yiyu Tan, Chihang Yau, Kaiman Lo, Paklun Mok, Anthony S. Fong  Processor Architectures, Design and Simulation 2005-WS-13
Moscu Panainte, Elena
2005
Interprocedural Optimization for Dynamic Hardware Configurations Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis Reconfigurable System Design and Implementations 2005-WS-02
Moudgill, Mayan
2005
Sandbridge Software Tools John Glossner, Sean Dorward, Sanjay Jinturkar, Mayan Moudgill, Erdem Hokenek, Michael Schulte, Stamatis Vassiliadis   Processor Architectures, Design and Simulation 2005-WS-29
Müller-Schloer, C.
2005
Mixed Virtual/Real Prototypes for Incremental System Design – A Proof of Concept Stefan Eilers, C. Müller-Schloer System Level Design, Modeling and Simulation 2005-WS-49
Murgan, T.
2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques M. Glesner, H. Hinkelmann, T. Hollstein, L. S. Indrusiak, T. Murgan, A.M. Obeid, M. Petrov, T. Pionteck, P. Zipf  Reconfigurable System Design and Implementations 2005-WS-03
Najjar, Walid A.
2005
Power Efficient Instruction Caches for Embedded Systems Dinesh C. Suresh, Walid A. Najjar, Jun Yang Processor Architectures, Design and Simulation 2005-WS-20
Neto, Horácio C.
2005
Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping Ricardo Ferreira, João M. P. Cardoso, Andre Toledo, Horácio C. Neto  Reconfigurable System Design and Implementations 2005-WS-06
Noll, Tobias G.
2005
Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll  System Level Design, Modeling and Simulation 2005-WS-40
Obeid, A.M.
2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques M. Glesner, H. Hinkelmann, T. Hollstein, L. S. Indrusiak, T. Murgan, A.M. Obeid, M. Petrov, T. Pionteck, P. Zipf  Reconfigurable System Design and Implementations 2005-WS-03
Paakkulainen, Jani
2005
Tuning a Protocol Processor Architecture Towards DSP Operations Jani Paakkulainen, Seppo Virtanen, Jouni Isoaho Processor Architectures, Design and Simulation 2005-WS-15
Park, Moonju
2005
Fast Real-Time Job Selection with Resource Constraints Under Earliest Deadline First Sangchul Han, Moonju Park, Yookun Cho Processor Architectures, Design and Simulation 2005-WS-26
Park, Sangduck
2005
Compressed Swapping for NAND Flash Memory Based Embedded Systems Sangduck Park, Hyunjin Lim, Hoseok Chang, Wonyong Sung  Architectures and Implementations 2005-WS-34
Payá Vayá, Guillermo
2005
RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration Guillermo Payá Vayá, Javier Martín Langerwerf, Peter Pirsch Reconfigurable System Design and Implementations 2005-WS-05
Petrov, M.
2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques M. Glesner, H. Hinkelmann, T. Hollstein, L. S. Indrusiak, T. Murgan, A.M. Obeid, M. Petrov, T. Pionteck, P. Zipf  Reconfigurable System Design and Implementations 2005-WS-03
Pimentel, Andy D.
2005
A Case for Visualization-Integrated System-Level Design Space Exploration Andy D. Pimentel  System Level Design, Modeling and Simulation 2005-WS-48
Pionteck, T.
2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques M. Glesner, H. Hinkelmann, T. Hollstein, L. S. Indrusiak, T. Murgan, A.M. Obeid, M. Petrov, T. Pionteck, P. Zipf  Reconfigurable System Design and Implementations 2005-WS-03
Pirsch, Peter
2005
RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration Guillermo Payá Vayá, Javier Martín Langerwerf, Peter Pirsch Reconfigurable System Design and Implementations 2005-WS-05
Pitkänen, Teemu
2005
Hardware Cost Estimation for Application-Specific Processor Design Teemu Pitkänen, Tommi Rantanen, Andrea Cilio, Jarmo Takala  Processor Architectures, Design and Simulation 2005-WS-23
Plosila, Juha
2005
Formal Specification of a Protocol Processor Tomi Westerlund, Juha Plosila Processor Architectures, Design and Simulation 2005-WS-14
Punkka, Konsta
2005
A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms David Guevorkian, Petri Liuha, Aki Launiainen, Konsta Punkka, Ville Lappalainen  Architectures and Implementations 2005-WS-35
Rantanen, Tommi
2005
Hardware Cost Estimation for Application-Specific Processor Design Teemu Pitkänen, Tommi Rantanen, Andrea Cilio, Jarmo Takala  Processor Architectures, Design and Simulation 2005-WS-23
Reilly, D.
2005
Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms John McAllister, Roger Woods, D. Reilly, Scott Fischaber, R. Hasson  System Level Design, Modeling and Simulation 2005-WS-44
Riihimäki, Jouni
2005
Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context Erno Salminen, Tero Kangas, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, Timo D. Hämäläinen   Architectures and Implementations 2005-WS-38
Robelly, J. P.
2005
Two-Dimensional Fast Cosine Transform for Vector-STA Architectures J. P. Robelly, A. Lehmann, Gerhard Fettweis Reconfigurable System Design and Implementations 2005-WS-08
Ruckdeschel, Holger
2005
Automatic FIR Filter Generation for FPGAs Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich  Reconfigurable System Design and Implementations 2005-WS-07
Sair, Suleyman
2005
Exploiting Intra-function Correlation with the Global History Stack Fei Gao, Suleyman Sair Processor Architectures, Design and Simulation 2005-WS-19
Salminen, Erno
2005
Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context Erno Salminen, Tero Kangas, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, Timo D. Hämäläinen   Architectures and Implementations 2005-WS-38
Sauer, Christian
2005
SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC Sören Sonntag, Matthias Gries, Christian Sauer System Level Design, Modeling and Simulation 2005-WS-46
Schulte, Michael
2005
Sandbridge Software Tools John Glossner, Sean Dorward, Sanjay Jinturkar, Mayan Moudgill, Erdem Hokenek, Michael Schulte, Stamatis Vassiliadis   Processor Architectures, Design and Simulation 2005-WS-29
Shim, Sunghoon
2005
First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption Cheol Hong Kim, Sunghoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon  Processor Architectures, Design and Simulation 2005-WS-12
Shim, Sunghoon
2005
Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic Sunghoon Shim, Jong Wook Kwak, Cheol Hong Kim, Sung Tae Jhang, Chu Shik Jhon  Processor Architectures, Design and Simulation 2005-WS-18
Silven, Olli
2005
Observations on Power-Efficiency Trends in Mobile Communication Devices Olli Silven, Kari Jyrkkä Processor Architectures, Design and Simulation 2005-WS-16
Sima, Mihai
2005
CORDIC-Augmented Sandbridge Processor for Channel Equalization Mihai Sima, John Glossner, Daniel Iancu, Hua Ye, Andrei Iancu, A. Joseph Hoane   Processor Architectures, Design and Simulation 2005-WS-17
Simonson, Lucanus J.
2005
Micro-architecture Performance Estimation by Formula Lucanus J. Simonson, Lei He Processor Architectures, Design and Simulation 2005-WS-21
Sinha, Purnendu
2005
A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems Philippe Marchand, Purnendu Sinha Architectures and Implementations 2005-WS-30
Song, Hong
2005
A Programming Model for an Embedded Media Processing Architecture Dan Zhang, Zeng-Zhi Li, Hong Song, Long Liu  Processor Architectures, Design and Simulation 2005-WS-27
Sonntag, Sören
2005
SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC Sören Sonntag, Matthias Gries, Christian Sauer System Level Design, Modeling and Simulation 2005-WS-46
Stavrou, Kyriakos
2005
DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor Kyriakos Stavrou, Paraskevas Evripidou, Pedro Trancoso Architectures and Implementations 2005-WS-39
Sung, Wonyong
2005
Compressed Swapping for NAND Flash Memory Based Embedded Systems Sangduck Park, Hyunjin Lim, Hoseok Chang, Wonyong Sung  Architectures and Implementations 2005-WS-34
Suresh, Dinesh C.
2005
Power Efficient Instruction Caches for Embedded Systems Dinesh C. Suresh, Walid A. Najjar, Jun Yang Processor Architectures, Design and Simulation 2005-WS-20
Taglietti, Leonardo
2005
Automatic ADL-Based Assembler Generation for ASIP Programming Support Leonardo Taglietti, José O. Carlomagno Filho, Daniel C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos  Processor Architectures, Design and Simulation 2005-WS-28
Takala, Jarmo
2005
Hardware Cost Estimation for Application-Specific Processor Design Teemu Pitkänen, Tommi Rantanen, Andrea Cilio, Jarmo Takala  Processor Architectures, Design and Simulation 2005-WS-23
Tan, Yiyu
2005
A Novel JAVA Processor for Embedded Devices Yiyu Tan, Chihang Yau, Kaiman Lo, Paklun Mok, Anthony S. Fong  Processor Architectures, Design and Simulation 2005-WS-13
Teich, Jürgen
2005
Automatic FIR Filter Generation for FPGAs Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich  Reconfigurable System Design and Implementations 2005-WS-07
Temmerman, Marijn
2005
Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications Marijn Temmerman, Edgar G. Daylight, Francky Catthoor, Serge Demeyer, Tom Dhaene  System Level Design, Modeling and Simulation 2005-WS-47
Toledo, Andre
2005
Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping Ricardo Ferreira, João M. P. Cardoso, Andre Toledo, Horácio C. Neto  Reconfigurable System Design and Implementations 2005-WS-06
Trancoso, Pedro
2005
DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor Kyriakos Stavrou, Paraskevas Evripidou, Pedro Trancoso Architectures and Implementations 2005-WS-39
van Royen, Ruben
2005
Generating Stream Based Code from Plain C Marcel Beemster, Hans van Someren, Liam Fitzpatrick, Ruben van Royen  Processor Architectures, Design and Simulation 2005-WS-25
van Someren, Hans
2005
Generating Stream Based Code from Plain C Marcel Beemster, Hans van Someren, Liam Fitzpatrick, Ruben van Royen  Processor Architectures, Design and Simulation 2005-WS-25
Vandeputte, Frederik
2005
Offline Phase Analysis and Optimization for Multi-configuration Processors Frederik Vandeputte, Lieven Eeckhout, Koen De Bosschere Processor Architectures, Design and Simulation 2005-WS-22
Vassiliadis, Stamatis
2005
Interprocedural Optimization for Dynamic Hardware Configurations Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis Reconfigurable System Design and Implementations 2005-WS-02
Vassiliadis, Stamatis
2005
Reconfigurable Multiple Operation Array Humberto Calderón, Stamatis Vassiliadis Reconfigurable System Design and Implementations 2005-WS-04
Vassiliadis, Stamatis
2005
Flux Caches: What Are They and Are They Useful? Georgi N. Gaydadjiev, Stamatis Vassiliadis Processor Architectures, Design and Simulation 2005-WS-11
Vassiliadis, Stamatis
2005
Sandbridge Software Tools John Glossner, Sean Dorward, Sanjay Jinturkar, Mayan Moudgill, Erdem Hokenek, Michael Schulte, Stamatis Vassiliadis   Processor Architectures, Design and Simulation 2005-WS-29
Virtanen, Seppo
2005
Tuning a Protocol Processor Architecture Towards DSP Operations Jani Paakkulainen, Seppo Virtanen, Jouni Isoaho Processor Architectures, Design and Simulation 2005-WS-15
von Sydow, Thorsten
2005
Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll  System Level Design, Modeling and Simulation 2005-WS-40
Westerlund, Tomi
2005
Formal Specification of a Protocol Processor Tomi Westerlund, Juha Plosila Processor Architectures, Design and Simulation 2005-WS-14
Woods, Roger
2005
Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms John McAllister, Roger Woods, D. Reilly, Scott Fischaber, R. Hasson  System Level Design, Modeling and Simulation 2005-WS-44
Yan, Guiying
2005
A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan  Architectures and Implementations 2005-WS-37
Yang, Jun
2005
Power Efficient Instruction Caches for Embedded Systems Dinesh C. Suresh, Walid A. Najjar, Jun Yang Processor Architectures, Design and Simulation 2005-WS-20
Yau, Chihang
2005
A Novel JAVA Processor for Embedded Devices Yiyu Tan, Chihang Yau, Kaiman Lo, Paklun Mok, Anthony S. Fong  Processor Architectures, Design and Simulation 2005-WS-13
Ye, Hua
2005
CORDIC-Augmented Sandbridge Processor for Channel Equalization Mihai Sima, John Glossner, Daniel Iancu, Hua Ye, Andrei Iancu, A. Joseph Hoane   Processor Architectures, Design and Simulation 2005-WS-17
Yi, Jongsu
2005
Real-Time Stereo Vision on a Reconfigurable System SungHwan Lee, Jongsu Yi, JunSeong Kim Architectures and Implementations 2005-WS-32
Zhang, Chunhui
2005
A Scalable Embedded JPEG2000 Architecture Chunhui Zhang, Yun Long, Fadi J. Kurdahi Architectures and Implementations 2005-WS-36
Zhang, Dan
2005
A Programming Model for an Embedded Media Processing Architecture Dan Zhang, Zeng-Zhi Li, Hong Song, Long Liu  Processor Architectures, Design and Simulation 2005-WS-27
Zipf, P.
2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques M. Glesner, H. Hinkelmann, T. Hollstein, L. S. Indrusiak, T. Murgan, A.M. Obeid, M. Petrov, T. Pionteck, P. Zipf  Reconfigurable System Design and Implementations 2005-WS-03
Zissulescu, Claudiu
2005
FPL-3E: Towards Language Support for Reconfigurable Packet Processing Mihai Lucian Cristea, Claudiu Zissulescu, Ed F. Deprettere, Herbert Bos  Reconfigurable System Design and Implementations 2005-WS-10
Agarwal, Nainesh
2006
Efficient Automated Clock Gating Using CoDeL Nainesh Agarwal, Nikitas J.  Dimopoulos System Design and Modeling 2006-WS-10
Agis, Rodrigo
2006
Real-Time Embedded System for Rear-View Mirror Overtaking Car Monitoring Javier Díaz, Eduardo Ros, Sonia Mota, Rodrigo Agis  Architectures and Implementations 2006-WS-39
Alho, Timo
2006
Security in Wireless Sensor Networks: Considerations and Experiments Panu Hämäläinen, Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensor Networks 2006-WS-18
Antonopoulos, Alexandros
2006
Preventing Denial-of-Service Attacks in Shared CMP Caches Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Alexandros Antonopoulos, Dimitrios Serpanos  Dependable Computing 2006-WS-37
Arpinen, Tero
2006
Automated Distribution of UML 2.0 Designed Applications to a Configurable Multiprocessor Platform Mikko Setälä, Petri Kukkala, Tero Arpinen, Marko Hännikäinen, Timo D. Hämäläinen  System Design and Modeling 2006-WS-05
Auguin, Michel
2006
Energy Optimization of a Multi-bank Main Memory Hanene Ben Fradj, Sébastien Icart, Cécile Belleudy, Michel Auguin  Processor Design 2006-WS-21
Baniasadi, Amirali
2006
Reducing Execution Unit Leakage Power in Embedded Processors Houman Homayoun, Amirali Baniasadi Processor Design 2006-WS-31
Beck, Antonio Carlos S.
2006
Advantages of Java Processors in Cache Performance and Power for Embedded Applications Antonio Carlos S. Beck, Mateus B. Rutzig, Luigi Carro Processor Design 2006-WS-33
Becker, Daniel
2006
Hybrid Functional and Instruction Level Power Modeling for Embedded Processors Holger Blume, Daniel Becker, Martin Botteck, Jörg Brakensiek, Tobias G. Noll  Processor Design 2006-WS-23
Belleudy, Cécile
2006
Energy Optimization of a Multi-bank Main Memory Hanene Ben Fradj, Sébastien Icart, Cécile Belleudy, Michel Auguin  Processor Design 2006-WS-21
Benini, Luca
2006
Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations Manish Verma, Lars Wehmeyer, Robert Pyka, Peter Marwedel, Luca Benini  Processor Design 2006-WS-29
Berbers, Yolande
2006
Towards a Transformation Chain Modeling Language Bert Vanhooff, Stefan Van Baelen, Aram Hovsepyan, Wouter Joosen, Yolande Berbers  System Design and Modeling 2006-WS-06
Berbers, Yolande
2006
Key Research Challenges for Successfully Applying MDD Within Real-Time Embedded Software Development Aram Hovsepyan, Stefan Van Baelen, Bert Vanhooff, Wouter Joosen, Yolande Berbers  System Design and Modeling 2006-WS-07
Berekovi?, Mladen
2006
A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme Mladen Berekovi?, Tim Niggemeier Processor Design 2006-WS-30
Bhattacharyya, Shuvra S.
2006
Energy-Driven Partitioning of Signal Processing Algorithms in Sensor Networks Dong-Ik Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya, Neil Goldsman  Wireless Sensor Networks 2006-WS-16
Blume, Holger
2006
Hybrid Functional and Instruction Level Power Modeling for Embedded Processors Holger Blume, Daniel Becker, Martin Botteck, Jörg Brakensiek, Tobias G. Noll  Processor Design 2006-WS-23
Botteck, Martin
2006
Hybrid Functional and Instruction Level Power Modeling for Embedded Processors Holger Blume, Daniel Becker, Martin Botteck, Jörg Brakensiek, Tobias G. Noll  Processor Design 2006-WS-23
Bountas, Dimitrios
2006
CARROT – A Tool for Fast and Accurate Soft Error Rate Estimation Dimitrios Bountas, Georgios I. Stamoulis Dependable Computing 2006-WS-34
Bradac, Zdenek
2006
On Security of PAN Wireless Systems Ondrej Hyncica, Peter Kacz, Petr Fiedler, Zdenek Bradac, Pavel Kucera, Radimir Vrba   Wireless Sensor Networks 2006-WS-19
Brakensiek, Jörg
2006
Hybrid Functional and Instruction Level Power Modeling for Embedded Processors Holger Blume, Daniel Becker, Martin Botteck, Jörg Brakensiek, Tobias G. Noll  Processor Design 2006-WS-23
Brinkschulte, Uwe
2006
A Scheduling Strategy for a Real-Time Dependable Organic Middleware Uwe Brinkschulte, Alexander von Renteln, Mathias Pacher Dependable Computing 2006-WS-35
Carro, Luigi
2006
Advantages of Java Processors in Cache Performance and Power for Embedded Applications Antonio Carlos S. Beck, Mateus B. Rutzig, Luigi Carro Processor Design 2006-WS-33
Chaves, Ricardo
2006
Rescheduling for Optimized SHA-1 Calculation Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis  Architectures and Implementations 2006-WS-43
Cho, Kyoung-Rok
2006
Design of Asynchronous Embedded Processor with New Ternary Data Encoding Scheme Je-Hoon Lee, Eun-Ju Choi, Kyoung-Rok Cho Architectures and Implementations 2006-WS-40
Choi, Eun-Ju
2006
Design of Asynchronous Embedded Processor with New Ternary Data Encoding Scheme Je-Hoon Lee, Eun-Ju Choi, Kyoung-Rok Cho Architectures and Implementations 2006-WS-40
Choi, Jinsung
2006
Reconfigurable Platform for Digital Convergence Terminals Jinsung Choi  SAMOS VI - Keynote 2006-WS-01
Chung, Ki-Dong
2006
A Flash File System to Support Fast Mounting for NAND Flash Memory Based Embedded Systems Song-Hwa Park, Tae-Hoon Lee, Ki-Dong Chung Architectures and Implementations 2006-WS-42
Corporaal, Henk
2006
Probabilistic Modelling and Evaluation of Soft Real-Time Embedded Systems Oana Florescu, Menno de Hoon, Jeroen Voeten, Henk Corporaal  Processor Design 2006-WS-22
Cotofana, Sorin Dan
2006
High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology Cor Meenderinck, Sorin Dan Cotofana Architectures and Implementations 2006-WS-45
da Cunha, Adriano B.
2006
Designing Wireless Sensor Nodes Marcos A. M. Vieira, Adriano B. da Cunha, Diógenes C. da Silva Wireless Sensor Networks 2006-WS-12
da Cunha, Adriano B.
2006
An Approach for the Reduction of Power Consumption in Sensor Nodes of Wireless Sensor Networks: Case Analysis of Mica2 Adriano B. da Cunha, Diógenes C. da Silva Wireless Sensor Networks 2006-WS-15
da Silva, Diógenes C.
2006
Designing Wireless Sensor Nodes Marcos A. M. Vieira, Adriano B. da Cunha, Diógenes C. da Silva Wireless Sensor Networks 2006-WS-12
da Silva, Diógenes C.
2006
An Approach for the Reduction of Power Consumption in Sensor Nodes of Wireless Sensor Networks: Case Analysis of Mica2 Adriano B. da Cunha, Diógenes C. da Silva Wireless Sensor Networks 2006-WS-15
Dai, Rui
2006
Mining Dynamic Document Spaces with Massively Parallel Embedded Processors Jan W. M. Jacobs, Rui Dai, Gerard J. M. Smit System Design and Modeling 2006-WS-09
de Hoon, Menno
2006
Probabilistic Modelling and Evaluation of Soft Real-Time Embedded Systems Oana Florescu, Menno de Hoon, Jeroen Voeten, Henk Corporaal  Processor Design 2006-WS-22
de Langen, Klaas-Jan
2006
Fault-Tolerant Bus System for Airbag Sensors and Actuators Klaas-Jan de Langen  Embedded Sensor Systems 2006-WS-49
Díaz, Javier
2006
Real-Time Embedded System for Rear-View Mirror Overtaking Car Monitoring Javier Díaz, Eduardo Ros, Sonia Mota, Rodrigo Agis  Architectures and Implementations 2006-WS-39
Dimopoulos, Nikitas J. 
2006
Efficient Automated Clock Gating Using CoDeL Nainesh Agarwal, Nikitas J.  Dimopoulos System Design and Modeling 2006-WS-10
Dutt, Nikil
2006
Domain-Specific Modeling of Power Aware Distributed Real-Time Embedded Systems Gabor Madl, Nikil Dutt System Design and Modeling 2006-WS-08
Feldhofer, Martin
2006
Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box Stefan Tillich, Martin Feldhofer, Johann Großschädl Architectures and Implementations 2006-WS-46
Fettweis, Gerhard
2006
An Optimization Methodology for Memory Allocation and Task Scheduling in SoCs Via Linear Programming Bastian Ristau, Gerhard Fettweis System Design and Modeling 2006-WS-11
Fiedler, Petr
2006
On Security of PAN Wireless Systems Ondrej Hyncica, Peter Kacz, Petr Fiedler, Zdenek Bradac, Pavel Kucera, Radimir Vrba   Wireless Sensor Networks 2006-WS-19
Florescu, Oana
2006
Probabilistic Modelling and Evaluation of Soft Real-Time Embedded Systems Oana Florescu, Menno de Hoon, Jeroen Voeten, Henk Corporaal  Processor Design 2006-WS-22
Fradj, Hanene Ben
2006
Energy Optimization of a Multi-bank Main Memory Hanene Ben Fradj, Sébastien Icart, Cécile Belleudy, Michel Auguin  Processor Design 2006-WS-21
French, Paddy J.
2006
Integrated Microsystems in Industrial Applications Paddy J. French  Embedded Sensor Systems 2006-WS-47
Gaydadjiev, Georgi N.
2006
SAD Prefetching for MPEG4 Using Flux Caches Georgi N. Gaydadjiev, Stamatis Vassiliadis Processor Design 2006-WS-26
Glossner, John
2006
Software Implementation of WiMAX on the Sandbridge SandBlaster Platform Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala  Architectures and Implementations 2006-WS-44
Goldsman, Neil
2006
Energy-Driven Partitioning of Signal Processing Algorithms in Sensor Networks Dong-Ik Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya, Neil Goldsman  Wireless Sensor Networks 2006-WS-16
Goratti, Leonardo
2006
Preamble Sense Multiple Access (PSMA) for Impulse Radio Ultra Wideband Sensor Networks Jussi Haapola, Leonardo Goratti, Isameldin Suliman, Alberto Rabbachin  Wireless Sensor Networks 2006-WS-17
Großschädl, Johann
2006
Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box Stefan Tillich, Martin Feldhofer, Johann Großschädl Architectures and Implementations 2006-WS-46
Haapola, Jussi
2006
Preamble Sense Multiple Access (PSMA) for Impulse Radio Ultra Wideband Sensor Networks Jussi Haapola, Leonardo Goratti, Isameldin Suliman, Alberto Rabbachin  Wireless Sensor Networks 2006-WS-17
Hagedoorn, Arend
2006
A Solid-State 2-D Wind Sensor K. A. A.  Makinwa, Johan H. Huijsing, Arend Hagedoorn Embedded Sensor Systems 2006-WS-48
Hama, Kotaro
2006
Autonomous Construction Technology of Community for Achieving High Assurance Service Kotaro Hama, Yuji Horikoshi, Yosuke Sugiyama, Kinji Mori  Dependable Computing 2006-WS-36
Hämäläinen, Panu
2006
Security in Wireless Sensor Networks: Considerations and Experiments Panu Hämäläinen, Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensor Networks 2006-WS-18
Hämäläinen, Timo D.
2006
Automated Distribution of UML 2.0 Designed Applications to a Configurable Multiprocessor Platform Mikko Setälä, Petri Kukkala, Tero Arpinen, Marko Hännikäinen, Timo D. Hämäläinen  System Design and Modeling 2006-WS-05
Hämäläinen, Timo D.
2006
Design, Implementation, and Experiments on Outdoor Deployment of Wireless Sensor Network for Environmental Monitoring Jukka Suhonen, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensor Networks 2006-WS-13
Hämäläinen, Timo D.
2006
Security in Wireless Sensor Networks: Considerations and Experiments Panu Hämäläinen, Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensor Networks 2006-WS-18
Haneda, Masayo
2006
Code Size Reduction by Compiler Tuning Masayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff Processor Design 2006-WS-20
Hännikäinen, Marko
2006
Automated Distribution of UML 2.0 Designed Applications to a Configurable Multiprocessor Platform Mikko Setälä, Petri Kukkala, Tero Arpinen, Marko Hännikäinen, Timo D. Hämäläinen  System Design and Modeling 2006-WS-05
Hännikäinen, Marko
2006
Design, Implementation, and Experiments on Outdoor Deployment of Wireless Sensor Network for Environmental Monitoring Jukka Suhonen, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensor Networks 2006-WS-13
Hännikäinen, Marko
2006
Security in Wireless Sensor Networks: Considerations and Experiments Panu Hämäläinen, Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensor Networks 2006-WS-18
Heikkinen, Jari
2006
Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform Teemu Pitkänen, Risto Mäkinen, Jari Heikkinen, Tero Partanen, Jarmo Takala  Processor Design 2006-WS-24
Heikkinen, Jari
2006
Effects of Program Compression Jari Heikkinen, Jarmo Takala Processor Design 2006-WS-27
Holsmark, Rickard
2006
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures Maurizio Palesi, Shashi Kumar, Rickard Holsmark Architectures and Implementations 2006-WS-38
Homayoun, Houman
2006
Reducing Execution Unit Leakage Power in Embedded Processors Houman Homayoun, Amirali Baniasadi Processor Design 2006-WS-31
Horikoshi, Yuji
2006
Autonomous Construction Technology of Community for Achieving High Assurance Service Kotaro Hama, Yuji Horikoshi, Yosuke Sugiyama, Kinji Mori  Dependable Computing 2006-WS-36
Hovsepyan, Aram
2006
Towards a Transformation Chain Modeling Language Bert Vanhooff, Stefan Van Baelen, Aram Hovsepyan, Wouter Joosen, Yolande Berbers  System Design and Modeling 2006-WS-06
Hovsepyan, Aram
2006
Key Research Challenges for Successfully Applying MDD Within Real-Time Embedded Software Development Aram Hovsepyan, Stefan Van Baelen, Bert Vanhooff, Wouter Joosen, Yolande Berbers  System Design and Modeling 2006-WS-07
Huijsing, Johan H.
2006
A Solid-State 2-D Wind Sensor K. A. A.  Makinwa, Johan H. Huijsing, Arend Hagedoorn Embedded Sensor Systems 2006-WS-48
Hyncica, Ondrej
2006
On Security of PAN Wireless Systems Ondrej Hyncica, Peter Kacz, Petr Fiedler, Zdenek Bradac, Pavel Kucera, Radimir Vrba   Wireless Sensor Networks 2006-WS-19
Iancu, Andrei
2006
Software Implementation of WiMAX on the Sandbridge SandBlaster Platform Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala  Architectures and Implementations 2006-WS-44
Iancu, Daniel
2006
Software Implementation of WiMAX on the Sandbridge SandBlaster Platform Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala  Architectures and Implementations 2006-WS-44
Icart, Sébastien
2006
Energy Optimization of a Multi-bank Main Memory Hanene Ben Fradj, Sébastien Icart, Cécile Belleudy, Michel Auguin  Processor Design 2006-WS-21
Iranpour, Ali
2006
Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors Ali Iranpour, Krzysztof Kuchcinski Processor Design 2006-WS-32
Jääskeläinen, Pekka
2006
Software Pipelining Support for Transport Triggered Architecture Processors Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala  Processor Design 2006-WS-25
Jacobs, Jan W. M.
2006
Mining Dynamic Document Spaces with Massively Parallel Embedded Processors Jan W. M. Jacobs, Rui Dai, Gerard J. M. Smit System Design and Modeling 2006-WS-09
Järvinen, Tuomas
2006
Software Pipelining Support for Transport Triggered Architecture Processors Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala  Processor Design 2006-WS-25
Joosen, Wouter
2006
Towards a Transformation Chain Modeling Language Bert Vanhooff, Stefan Van Baelen, Aram Hovsepyan, Wouter Joosen, Yolande Berbers  System Design and Modeling 2006-WS-06
Joosen, Wouter
2006
Key Research Challenges for Successfully Applying MDD Within Real-Time Embedded Software Development Aram Hovsepyan, Stefan Van Baelen, Bert Vanhooff, Wouter Joosen, Yolande Berbers  System Design and Modeling 2006-WS-07
Kacz, Peter
2006
On Security of PAN Wireless Systems Ondrej Hyncica, Peter Kacz, Petr Fiedler, Zdenek Bradac, Pavel Kucera, Radimir Vrba   Wireless Sensor Networks 2006-WS-19
Kaxiras, Stefanos
2006
Preventing Denial-of-Service Attacks in Shared CMP Caches Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Alexandros Antonopoulos, Dimitrios Serpanos  Dependable Computing 2006-WS-37
Keramidas, Georgios
2006
Preventing Denial-of-Service Attacks in Shared CMP Caches Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Alexandros Antonopoulos, Dimitrios Serpanos  Dependable Computing 2006-WS-37
Kim, Dae-Hwan
2006
Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors Dae-Hwan Kim, Hyuk-Jae Lee Processor Design 2006-WS-28
Kim, Dae-Won
2006
LATONA: An Advanced Server Architecture for Ubiquitous Sensor Network Chi-Hoon Shin, Soo-Cheol Oh, Dae-Won Kim, Sun-Wook Kim, Kyoung Park, Sung-Woon Kim   Wireless Sensor Networks 2006-WS-14
Kim, Sun-Wook
2006
LATONA: An Advanced Server Architecture for Ubiquitous Sensor Network Chi-Hoon Shin, Soo-Cheol Oh, Dae-Won Kim, Sun-Wook Kim, Kyoung Park, Sung-Woon Kim   Wireless Sensor Networks 2006-WS-14
Kim, Sung-Woon
2006
LATONA: An Advanced Server Architecture for Ubiquitous Sensor Network Chi-Hoon Shin, Soo-Cheol Oh, Dae-Won Kim, Sun-Wook Kim, Kyoung Park, Sung-Woon Kim   Wireless Sensor Networks 2006-WS-14
Knijnenburg, Peter M. W.
2006
Code Size Reduction by Compiler Tuning Masayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff Processor Design 2006-WS-20
Ko, Dong-Ik
2006
Energy-Driven Partitioning of Signal Processing Algorithms in Sensor Networks Dong-Ik Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya, Neil Goldsman  Wireless Sensor Networks 2006-WS-16
Kohvakka, Mikko
2006
Design, Implementation, and Experiments on Outdoor Deployment of Wireless Sensor Network for Environmental Monitoring Jukka Suhonen, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensor Networks 2006-WS-13
Kotlyar, Vladimir
2006
Software Implementation of WiMAX on the Sandbridge SandBlaster Platform Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala  Architectures and Implementations 2006-WS-44
Kucera, Pavel
2006
On Security of PAN Wireless Systems Ondrej Hyncica, Peter Kacz, Petr Fiedler, Zdenek Bradac, Pavel Kucera, Radimir Vrba   Wireless Sensor Networks 2006-WS-19
Kuchcinski, Krzysztof
2006
Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors Ali Iranpour, Krzysztof Kuchcinski Processor Design 2006-WS-32
Kukkala, Petri
2006
Automated Distribution of UML 2.0 Designed Applications to a Configurable Multiprocessor Platform Mikko Setälä, Petri Kukkala, Tero Arpinen, Marko Hännikäinen, Timo D. Hämäläinen  System Design and Modeling 2006-WS-05
Kumar, Shashi
2006
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures Maurizio Palesi, Shashi Kumar, Rickard Holsmark Architectures and Implementations 2006-WS-38
Kuorilehto, Mauri
2006
Security in Wireless Sensor Networks: Considerations and Experiments Panu Hämäläinen, Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensor Networks 2006-WS-18
Kuzmanov, Georgi
2006
Rescheduling for Optimized SHA-1 Calculation Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis  Architectures and Implementations 2006-WS-43
Lee, Hyuk-Jae
2006
Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors Dae-Hwan Kim, Hyuk-Jae Lee Processor Design 2006-WS-28
Lee, Je-Hoon
2006
Design of Asynchronous Embedded Processor with New Ternary Data Encoding Scheme Je-Hoon Lee, Eun-Ju Choi, Kyoung-Rok Cho Architectures and Implementations 2006-WS-40
Lee, Tae-Hoon
2006
A Flash File System to Support Fast Mounting for NAND Flash Memory Based Embedded Systems Song-Hwa Park, Tae-Hoon Lee, Ki-Dong Chung Architectures and Implementations 2006-WS-42
Madl, Gabor
2006
Domain-Specific Modeling of Power Aware Distributed Real-Time Embedded Systems Gabor Madl, Nikil Dutt System Design and Modeling 2006-WS-08
Mäkinen, Risto
2006
Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform Teemu Pitkänen, Risto Mäkinen, Jari Heikkinen, Tero Partanen, Jarmo Takala  Processor Design 2006-WS-24
Makinwa, K. A. A. 
2006
A Solid-State 2-D Wind Sensor K. A. A.  Makinwa, Johan H. Huijsing, Arend Hagedoorn Embedded Sensor Systems 2006-WS-48
Marwedel, Peter
2006
Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations Manish Verma, Lars Wehmeyer, Robert Pyka, Peter Marwedel, Luca Benini  Processor Design 2006-WS-29
Meenderinck, Cor
2006
High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology Cor Meenderinck, Sorin Dan Cotofana Architectures and Implementations 2006-WS-45
Mori, Kinji
2006
Autonomous Construction Technology of Community for Achieving High Assurance Service Kotaro Hama, Yuji Horikoshi, Yosuke Sugiyama, Kinji Mori  Dependable Computing 2006-WS-36
Mota, Sonia
2006
Real-Time Embedded System for Rear-View Mirror Overtaking Car Monitoring Javier Díaz, Eduardo Ros, Sonia Mota, Rodrigo Agis  Architectures and Implementations 2006-WS-39
Nacer, Gary
2006
Software Implementation of WiMAX on the Sandbridge SandBlaster Platform Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala  Architectures and Implementations 2006-WS-44
Niggemeier, Tim
2006
A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme Mladen Berekovi?, Tim Niggemeier Processor Design 2006-WS-30
Noll, Tobias G.
2006
Hybrid Functional and Instruction Level Power Modeling for Embedded Processors Holger Blume, Daniel Becker, Martin Botteck, Jörg Brakensiek, Tobias G. Noll  Processor Design 2006-WS-23
Oh, Soo-Cheol
2006
LATONA: An Advanced Server Architecture for Ubiquitous Sensor Network Chi-Hoon Shin, Soo-Cheol Oh, Dae-Won Kim, Sun-Wook Kim, Kyoung Park, Sung-Woon Kim   Wireless Sensor Networks 2006-WS-14
Oliver, Ian
2006
A UML Profile for Asynchronous Hardware Design Kim Sandström, Ian Oliver System Design and Modeling 2006-WS-04
Pacher, Mathias
2006
A Scheduling Strategy for a Real-Time Dependable Organic Middleware Uwe Brinkschulte, Alexander von Renteln, Mathias Pacher Dependable Computing 2006-WS-35
Palesi, Maurizio
2006
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures Maurizio Palesi, Shashi Kumar, Rickard Holsmark Architectures and Implementations 2006-WS-38
Park, Kyoung
2006
LATONA: An Advanced Server Architecture for Ubiquitous Sensor Network Chi-Hoon Shin, Soo-Cheol Oh, Dae-Won Kim, Sun-Wook Kim, Kyoung Park, Sung-Woon Kim   Wireless Sensor Networks 2006-WS-14
Park, Song-Hwa
2006
A Flash File System to Support Fast Mounting for NAND Flash Memory Based Embedded Systems Song-Hwa Park, Tae-Hoon Lee, Ki-Dong Chung Architectures and Implementations 2006-WS-42
Partanen, Tero
2006
Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform Teemu Pitkänen, Risto Mäkinen, Jari Heikkinen, Tero Partanen, Jarmo Takala  Processor Design 2006-WS-24
Petoumenos, Pavlos
2006
Preventing Denial-of-Service Attacks in Shared CMP Caches Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Alexandros Antonopoulos, Dimitrios Serpanos  Dependable Computing 2006-WS-37
Pitkänen, Teemu
2006
Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform Teemu Pitkänen, Risto Mäkinen, Jari Heikkinen, Tero Partanen, Jarmo Takala  Processor Design 2006-WS-24
Pyka, Robert
2006
Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations Manish Verma, Lars Wehmeyer, Robert Pyka, Peter Marwedel, Luca Benini  Processor Design 2006-WS-29
Rabbachin, Alberto
2006
Preamble Sense Multiple Access (PSMA) for Impulse Radio Ultra Wideband Sensor Networks Jussi Haapola, Leonardo Goratti, Isameldin Suliman, Alberto Rabbachin  Wireless Sensor Networks 2006-WS-17
Raekallio, Juuso
2006
Interface Overheads in Embedded Multimedia Software Tero Rintaluoma, Olli Silven, Juuso Raekallio System Design and Modeling 2006-WS-03
Rintaluoma, Tero
2006
Interface Overheads in Embedded Multimedia Software Tero Rintaluoma, Olli Silven, Juuso Raekallio System Design and Modeling 2006-WS-03
Ristau, Bastian
2006
An Optimization Methodology for Memory Allocation and Task Scheduling in SoCs Via Linear Programming Bastian Ristau, Gerhard Fettweis System Design and Modeling 2006-WS-11
Ros, Eduardo
2006
Real-Time Embedded System for Rear-View Mirror Overtaking Car Monitoring Javier Díaz, Eduardo Ros, Sonia Mota, Rodrigo Agis  Architectures and Implementations 2006-WS-39
Rutzig, Mateus B.
2006
Advantages of Java Processors in Cache Performance and Power for Embedded Applications Antonio Carlos S. Beck, Mateus B. Rutzig, Luigi Carro Processor Design 2006-WS-33
Salmela, Perttu
2006
Software Pipelining Support for Transport Triggered Architecture Processors Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala  Processor Design 2006-WS-25
Sandström, Kim
2006
A UML Profile for Asynchronous Hardware Design Kim Sandström, Ian Oliver System Design and Modeling 2006-WS-04
Senthilvelan, Murugappan
2006
Software Implementation of WiMAX on the Sandbridge SandBlaster Platform Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala  Architectures and Implementations 2006-WS-44
Serpanos, Dimitrios
2006
Preventing Denial-of-Service Attacks in Shared CMP Caches Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras, Alexandros Antonopoulos, Dimitrios Serpanos  Dependable Computing 2006-WS-37
Setälä, Mikko
2006
Automated Distribution of UML 2.0 Designed Applications to a Configurable Multiprocessor Platform Mikko Setälä, Petri Kukkala, Tero Arpinen, Marko Hännikäinen, Timo D. Hämäläinen  System Design and Modeling 2006-WS-05
Shen, Chung-Ching
2006
Energy-Driven Partitioning of Signal Processing Algorithms in Sensor Networks Dong-Ik Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya, Neil Goldsman  Wireless Sensor Networks 2006-WS-16
Shin, Chi-Hoon
2006
LATONA: An Advanced Server Architecture for Ubiquitous Sensor Network Chi-Hoon Shin, Soo-Cheol Oh, Dae-Won Kim, Sun-Wook Kim, Kyoung Park, Sung-Woon Kim   Wireless Sensor Networks 2006-WS-14
Silven, Olli
2006
Interface Overheads in Embedded Multimedia Software Tero Rintaluoma, Olli Silven, Juuso Raekallio System Design and Modeling 2006-WS-03
Smit, Gerard J. M.
2006
Mining Dynamic Document Spaces with Massively Parallel Embedded Processors Jan W. M. Jacobs, Rui Dai, Gerard J. M. Smit System Design and Modeling 2006-WS-09
Sousa, Leonel
2006
Rescheduling for Optimized SHA-1 Calculation Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis  Architectures and Implementations 2006-WS-43
Stamoulis, Georgios I.
2006
CARROT – A Tool for Fast and Accurate Soft Error Rate Estimation Dimitrios Bountas, Georgios I. Stamoulis Dependable Computing 2006-WS-34
Sugiyama, Yosuke
2006
Autonomous Construction Technology of Community for Achieving High Assurance Service Kotaro Hama, Yuji Horikoshi, Yosuke Sugiyama, Kinji Mori  Dependable Computing 2006-WS-36
Suhonen, Jukka
2006
Design, Implementation, and Experiments on Outdoor Deployment of Wireless Sensor Network for Environmental Monitoring Jukka Suhonen, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensor Networks 2006-WS-13
Suliman, Isameldin
2006
Preamble Sense Multiple Access (PSMA) for Impulse Radio Ultra Wideband Sensor Networks Jussi Haapola, Leonardo Goratti, Isameldin Suliman, Alberto Rabbachin  Wireless Sensor Networks 2006-WS-17
Surducan, Emanoil
2006
Software Implementation of WiMAX on the Sandbridge SandBlaster Platform Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala  Architectures and Implementations 2006-WS-44
Surducan, Vasile
2006
Software Implementation of WiMAX on the Sandbridge SandBlaster Platform Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala  Architectures and Implementations 2006-WS-44
Takala, Jarmo
2006
Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform Teemu Pitkänen, Risto Mäkinen, Jari Heikkinen, Tero Partanen, Jarmo Takala  Processor Design 2006-WS-24
Takala, Jarmo
2006
Software Pipelining Support for Transport Triggered Architecture Processors Perttu Salmela, Pekka Jääskeläinen, Tuomas Järvinen, Jarmo Takala  Processor Design 2006-WS-25
Takala, Jarmo
2006
Effects of Program Compression Jari Heikkinen, Jarmo Takala Processor Design 2006-WS-27
Takala, Jarmo
2006
Software Implementation of WiMAX on the Sandbridge SandBlaster Platform Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala  Architectures and Implementations 2006-WS-44
Tillich, Stefan
2006
Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box Stefan Tillich, Martin Feldhofer, Johann Großschädl Architectures and Implementations 2006-WS-46
Tsarchopoulos, Panagiotis
2006
European Research in Embedded Systems Panagiotis Tsarchopoulos  SAMOS VI - Keynote 2006-WS-02
Van Baelen, Stefan
2006
Towards a Transformation Chain Modeling Language Bert Vanhooff, Stefan Van Baelen, Aram Hovsepyan, Wouter Joosen, Yolande Berbers  System Design and Modeling 2006-WS-06
Van Baelen, Stefan
2006
Key Research Challenges for Successfully Applying MDD Within Real-Time Embedded Software Development Aram Hovsepyan, Stefan Van Baelen, Bert Vanhooff, Wouter Joosen, Yolande Berbers  System Design and Modeling 2006-WS-07
Vanhooff, Bert
2006
Towards a Transformation Chain Modeling Language Bert Vanhooff, Stefan Van Baelen, Aram Hovsepyan, Wouter Joosen, Yolande Berbers  System Design and Modeling 2006-WS-06
Vanhooff, Bert
2006
Key Research Challenges for Successfully Applying MDD Within Real-Time Embedded Software Development Aram Hovsepyan, Stefan Van Baelen, Bert Vanhooff, Wouter Joosen, Yolande Berbers  System Design and Modeling 2006-WS-07
Vassiliadis, Stamatis
2006
SAD Prefetching for MPEG4 Using Flux Caches Georgi N. Gaydadjiev, Stamatis Vassiliadis Processor Design 2006-WS-26
Vassiliadis, Stamatis
2006
Rescheduling for Optimized SHA-1 Calculation Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis  Architectures and Implementations 2006-WS-43
Verma, Manish
2006
Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations Manish Verma, Lars Wehmeyer, Robert Pyka, Peter Marwedel, Luca Benini  Processor Design 2006-WS-29
Vieira, Marcos A. M.
2006
Designing Wireless Sensor Nodes Marcos A. M. Vieira, Adriano B. da Cunha, Diógenes C. da Silva Wireless Sensor Networks 2006-WS-12
Voeten, Jeroen
2006
Probabilistic Modelling and Evaluation of Soft Real-Time Embedded Systems Oana Florescu, Menno de Hoon, Jeroen Voeten, Henk Corporaal  Processor Design 2006-WS-22
von Renteln, Alexander
2006
A Scheduling Strategy for a Real-Time Dependable Organic Middleware Uwe Brinkschulte, Alexander von Renteln, Mathias Pacher Dependable Computing 2006-WS-35
Vrba, Radimir
2006
On Security of PAN Wireless Systems Ondrej Hyncica, Peter Kacz, Petr Fiedler, Zdenek Bradac, Pavel Kucera, Radimir Vrba   Wireless Sensor Networks 2006-WS-19
Wehmeyer, Lars
2006
Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations Manish Verma, Lars Wehmeyer, Robert Pyka, Peter Marwedel, Luca Benini  Processor Design 2006-WS-29
Wijshoff, Harry A. G.
2006
Code Size Reduction by Compiler Tuning Masayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff Processor Design 2006-WS-20
Ye, Hua
2006
Software Implementation of WiMAX on the Sandbridge SandBlaster Platform Daniel Iancu, Hua Ye, Emanoil Surducan, Murugappan Senthilvelan, John Glossner, Vasile Surducan, Vladimir Kotlyar, Andrei Iancu, Gary Nacer, Jarmo Takala  Architectures and Implementations 2006-WS-44
Yun, SangKyun
2006
Hardware-Based IP Lookup Using n-Way Set Associative Memory and LPM Comparator SangKyun Yun  Architectures and Implementations 2006-WS-41
Aboelaze, M.
2006
Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors K. Ali, M. Aboelaze, S. Datta Energy Aware Processors 2006-IC-06
Acacio, Manuel E.
2006
On the Evaluation of Dense Chip-Multiprocessor Architectures Francisco J. Villa, Manuel E. Acacio, Jose M. Garcia Embedded Processors and Architectures 2006-IC-04
Aho, Eero
2006
Parallel Memory Implementation for Arbitrary Stride Accesses Eero Aho, Jarno Vanne, Timo D. Hämäläinen Embedded Processors and Architectures 2006-IC-01
Ali, K.
2006
Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors K. Ali, M. Aboelaze, S. Datta Energy Aware Processors 2006-IC-06
Ascia, Giuseppe
2006
An Efficient Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design Giuseppe Ascia, Vincenzo Catania, Alessandro G. di Nuovo, Maurizio Palesi, Davide Patti  High Level System Design and Simulation 2006-IC-17
Baniasadi, Amirali
2006
Area-Aware Optimizations for Resource Constrained Branch Predictors Exploited in Embedded Processors Babak Salamat, Amirali Baniasadi, Kaveh Jokar Deris Energy Aware Processors 2006-IC-08
Basten, Twan
2006
Profiling Driven Scenario Detection and Prediction for Multimedia Applications Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal Design Space Exploration (1) 2006-IC-10
Bhattacharyya, Shuvra S.
2006
Memory-constrained Block Processing Optimization for Synthesis of DSP Software Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya High Level System Design and Simulation 2006-IC-20
Borgio, Simone
2006
Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo   Design Space Exploration (2) 2006-IC-16
Bosisio, Davide
2006
Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo   Design Space Exploration (2) 2006-IC-16
Brockmeyer, Erik
2006
Pareto-Based Application Specification for MP-SoC Customized Run-Time Management Ch. Ykman-Couvreur, V. Nollet, Théodore Marescaux, Erik Brockmeyer, Francky Catthoor, Henk Corporaal   Design Space Exploration (1) 2006-IC-12
Catania, Vincenzo
2006
An Efficient Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design Giuseppe Ascia, Vincenzo Catania, Alessandro G. di Nuovo, Maurizio Palesi, Davide Patti  High Level System Design and Simulation 2006-IC-17
Catthoor, Francky
2006
Pareto-Based Application Specification for MP-SoC Customized Run-Time Management Ch. Ykman-Couvreur, V. Nollet, Théodore Marescaux, Erik Brockmeyer, Francky Catthoor, Henk Corporaal   Design Space Exploration (1) 2006-IC-12
Cheung, Peter Y.K.
2006
On-Chip Communication in Run-Time Assembled Reconfigurable Systems Pete Sedcole, Peter Y.K. Cheung, George A. Constantinides, Wayne Luk  Reconfigurable Processors and Applications of Embedded Systems 2006-IC-24
Constantinides, George A.
2006
On-Chip Communication in Run-Time Assembled Reconfigurable Systems Pete Sedcole, Peter Y.K. Cheung, George A. Constantinides, Wayne Luk  Reconfigurable Processors and Applications of Embedded Systems 2006-IC-24
Corporaal, Henk
2006
Profiling Driven Scenario Detection and Prediction for Multimedia Applications Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal Design Space Exploration (1) 2006-IC-10
Corporaal, Henk
2006
Pareto-Based Application Specification for MP-SoC Customized Run-Time Management Ch. Ykman-Couvreur, V. Nollet, Théodore Marescaux, Erik Brockmeyer, Francky Catthoor, Henk Corporaal   Design Space Exploration (1) 2006-IC-12
Cotofana, Sorin Dan
2006
Throughput optimization via cache partitioning for embedded multiprocessors Anca M. Molnos, Sorin Dan Cotofana, Marc J.M. Heijligers, Jos T. J. van Eijndhoven  Reconfigurable Processors and Applications of Embedded Systems 2006-IC-26
Datta, S.
2006
Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors K. Ali, M. Aboelaze, S. Datta Energy Aware Processors 2006-IC-06
Deris, Kaveh Jokar
2006
Area-Aware Optimizations for Resource Constrained Branch Predictors Exploited in Embedded Processors Babak Salamat, Amirali Baniasadi, Kaveh Jokar Deris Energy Aware Processors 2006-IC-08
di Nuovo, Alessandro G.
2006
An Efficient Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design Giuseppe Ascia, Vincenzo Catania, Alessandro G. di Nuovo, Maurizio Palesi, Davide Patti  High Level System Design and Simulation 2006-IC-17
Dimitroulakos, G.
2006
Performance Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path Michalis D. Galanis, G. Dimitroulakos, Costas E. Goutis Design Space Exploration (2) 2006-IC-13
Erbas, Cagkan
2006
On the Calibration of Abstract Performance Models for System-level Design Space Exploration Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas  Design Space Exploration (1) 2006-IC-11
Ferrandi, Fabrizio
2006
Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo   Design Space Exploration (2) 2006-IC-16
Galanis, Michalis D.
2006
Performance Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path Michalis D. Galanis, G. Dimitroulakos, Costas E. Goutis Design Space Exploration (2) 2006-IC-13
Garcia, Jose M.
2006
On the Evaluation of Dense Chip-Multiprocessor Architectures Francisco J. Villa, Manuel E. Acacio, Jose M. Garcia Embedded Processors and Architectures 2006-IC-04
Gawlowski, Dominik
2006
Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems Lech Jozwiak, Dominik Gawlowski, Aleksander Slusarczyk Reconfigurable Processors and Applications of Embedded Systems 2006-IC-25
Gheorghita, Stefan Valentin
2006
Profiling Driven Scenario Detection and Prediction for Multimedia Applications Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal Design Space Exploration (1) 2006-IC-10
Goudarzi, Maziar
2006
A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems Shaahin Hessabi, M. Modarressi, Maziar Goudarzi, H. Javanhemmat  Embedded Processors and Architectures 2006-IC-02
Goutis, Costas E.
2006
Performance Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path Michalis D. Galanis, G. Dimitroulakos, Costas E. Goutis Design Space Exploration (2) 2006-IC-13
Gurun, S.
2006
SimGate: Full-System, Cycle-Close Simulation of the Stargate Sensor Network Intermediate Node Y. Wen, S. Gurun, Chohan Navraj, R. Wolski, C. Krintz  High Level System Design and Simulation 2006-IC-19
Hämäläinen, Timo D.
2006
Parallel Memory Implementation for Arbitrary Stride Accesses Eero Aho, Jarno Vanne, Timo D. Hämäläinen Embedded Processors and Architectures 2006-IC-01
Haubelt, Christian
2006
Multi-Objective Topology Optimization for Networked Embedded Systems Thilo Streichert, Christian Haubelt, Jürgen Teich Design Space Exploration (2) 2006-IC-14
Heijligers, Marc J.M.
2006
Throughput optimization via cache partitioning for embedded multiprocessors Anca M. Molnos, Sorin Dan Cotofana, Marc J.M. Heijligers, Jos T. J. van Eijndhoven  Reconfigurable Processors and Applications of Embedded Systems 2006-IC-26
Herkersdorf, Andreas
2006
Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf  System and Network-on-Chip Platforms 2006-IC-22
Hessabi, Shaahin
2006
A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems Shaahin Hessabi, M. Modarressi, Maziar Goudarzi, H. Javanhemmat  Embedded Processors and Architectures 2006-IC-02
Holler, R.
2006
Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression H. Muhr, R. Holler High Level System Design and Simulation 2006-IC-18
Hu, Jie
2006
On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors Shuai Wang, Jie Hu, Sotirios G. Ziavras Embedded Processors and Architectures 2006-IC-03
Islam, Md. Mafijul
2006
Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations Md. Mafijul Islam, Per Stenstrom Energy Aware Processors 2006-IC-05
Javanhemmat, H.
2006
A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems Shaahin Hessabi, M. Modarressi, Maziar Goudarzi, H. Javanhemmat  Embedded Processors and Architectures 2006-IC-02
Jeschke, Hartwig
2006
Chip Size Estimation for SOC Design Space Exploration Hartwig Jeschke  Design Space Exploration (1) 2006-IC-09
Jozwiak, Lech
2006
Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems Lech Jozwiak, Dominik Gawlowski, Aleksander Slusarczyk Reconfigurable Processors and Applications of Embedded Systems 2006-IC-25
Ko, Ming-Yung
2006
Memory-constrained Block Processing Optimization for Synthesis of DSP Software Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya High Level System Design and Simulation 2006-IC-20
Krintz, C.
2006
SimGate: Full-System, Cycle-Close Simulation of the Stargate Sensor Network Intermediate Node Y. Wen, S. Gurun, Chohan Navraj, R. Wolski, C. Krintz  High Level System Design and Simulation 2006-IC-19
Lafond, Sebastien
2006
Static Energy Saving Through Multi-Bank Memory Architecture Sebastien Lafond, Johan Lilius Energy Aware Processors 2006-IC-07
Lilius, Johan
2006
Static Energy Saving Through Multi-Bank Memory Architecture Sebastien Lafond, Johan Lilius Energy Aware Processors 2006-IC-07
Luk, Wayne
2006
On-Chip Communication in Run-Time Assembled Reconfigurable Systems Pete Sedcole, Peter Y.K. Cheung, George A. Constantinides, Wayne Luk  Reconfigurable Processors and Applications of Embedded Systems 2006-IC-24
Marescaux, Théodore
2006
Pareto-Based Application Specification for MP-SoC Customized Run-Time Management Ch. Ykman-Couvreur, V. Nollet, Théodore Marescaux, Erik Brockmeyer, Francky Catthoor, Henk Corporaal   Design Space Exploration (1) 2006-IC-12
Meitinger, Michael
2006
Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf  System and Network-on-Chip Platforms 2006-IC-22
Merker, R.
2006
Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism R. Schaffer, R. Merker Design Space Exploration (2) 2006-IC-15
Modarressi, M.
2006
A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems Shaahin Hessabi, M. Modarressi, Maziar Goudarzi, H. Javanhemmat  Embedded Processors and Architectures 2006-IC-02
Molnos, Anca M.
2006
Throughput optimization via cache partitioning for embedded multiprocessors Anca M. Molnos, Sorin Dan Cotofana, Marc J.M. Heijligers, Jos T. J. van Eijndhoven  Reconfigurable Processors and Applications of Embedded Systems 2006-IC-26
Monchiero, Matteo
2006
Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo   Design Space Exploration (2) 2006-IC-16
Monchiero, Matteo
2006
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa  System and Network-on-Chip Platforms 2006-IC-21
Muhr, H.
2006
Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression H. Muhr, R. Holler High Level System Design and Simulation 2006-IC-18
Navraj, Chohan
2006
SimGate: Full-System, Cycle-Close Simulation of the Stargate Sensor Network Intermediate Node Y. Wen, S. Gurun, Chohan Navraj, R. Wolski, C. Krintz  High Level System Design and Simulation 2006-IC-19
Nollet, V.
2006
Pareto-Based Application Specification for MP-SoC Customized Run-Time Management Ch. Ykman-Couvreur, V. Nollet, Théodore Marescaux, Erik Brockmeyer, Francky Catthoor, Henk Corporaal   Design Space Exploration (1) 2006-IC-12
Ohlendorf, Rainer
2006
Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf  System and Network-on-Chip Platforms 2006-IC-22
Palermo, Gianluca
2006
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa  System and Network-on-Chip Platforms 2006-IC-21
Palesi, Maurizio
2006
An Efficient Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design Giuseppe Ascia, Vincenzo Catania, Alessandro G. di Nuovo, Maurizio Palesi, Davide Patti  High Level System Design and Simulation 2006-IC-17
Patti, Davide
2006
An Efficient Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design Giuseppe Ascia, Vincenzo Catania, Alessandro G. di Nuovo, Maurizio Palesi, Davide Patti  High Level System Design and Simulation 2006-IC-17
Pimentel, Andy D.
2006
On the Calibration of Abstract Performance Models for System-level Design Space Exploration Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas  Design Space Exploration (1) 2006-IC-11
Polstra, Simon
2006
On the Calibration of Abstract Performance Models for System-level Design Space Exploration Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas  Design Space Exploration (1) 2006-IC-11
Rauchfuss, Holm
2006
Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf  System and Network-on-Chip Platforms 2006-IC-22
Salamat, Babak
2006
Area-Aware Optimizations for Resource Constrained Branch Predictors Exploited in Embedded Processors Babak Salamat, Amirali Baniasadi, Kaveh Jokar Deris Energy Aware Processors 2006-IC-08
Santambrogio, Marco D.
2006
Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo   Design Space Exploration (2) 2006-IC-16
Schaffer, R.
2006
Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism R. Schaffer, R. Merker Design Space Exploration (2) 2006-IC-15
Sciuto, Donatella
2006
Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo   Design Space Exploration (2) 2006-IC-16
Sedcole, Pete
2006
On-Chip Communication in Run-Time Assembled Reconfigurable Systems Pete Sedcole, Peter Y.K. Cheung, George A. Constantinides, Wayne Luk  Reconfigurable Processors and Applications of Embedded Systems 2006-IC-24
Shen, Chung-Ching
2006
Memory-constrained Block Processing Optimization for Synthesis of DSP Software Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya High Level System Design and Simulation 2006-IC-20
Silvano, Cristina
2006
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa  System and Network-on-Chip Platforms 2006-IC-21
Slusarczyk, Aleksander
2006
Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems Lech Jozwiak, Dominik Gawlowski, Aleksander Slusarczyk Reconfigurable Processors and Applications of Embedded Systems 2006-IC-25
Sourdis, Ioannis
2006
FLUX Networks: Interconnects on Demand Stamatis Vassiliadis, Ioannis Sourdis System and Network-on-Chip Platforms 2006-IC-23
Stenstrom, Per
2006
Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations Md. Mafijul Islam, Per Stenstrom Energy Aware Processors 2006-IC-05
Streichert, Thilo
2006
Multi-Objective Topology Optimization for Networked Embedded Systems Thilo Streichert, Christian Haubelt, Jürgen Teich Design Space Exploration (2) 2006-IC-14
Teich, Jürgen
2006
Multi-Objective Topology Optimization for Networked Embedded Systems Thilo Streichert, Christian Haubelt, Jürgen Teich Design Space Exploration (2) 2006-IC-14
Thompson, Mark
2006
On the Calibration of Abstract Performance Models for System-level Design Space Exploration Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas  Design Space Exploration (1) 2006-IC-11
Tumeo, Antonino
2006
Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA Simone Borgio, Davide Bosisio, Fabrizio Ferrandi, Matteo Monchiero, Marco D. Santambrogio, Donatella Sciuto, Antonino Tumeo   Design Space Exploration (2) 2006-IC-16
van Eijndhoven, Jos T. J.
2006
Throughput optimization via cache partitioning for embedded multiprocessors Anca M. Molnos, Sorin Dan Cotofana, Marc J.M. Heijligers, Jos T. J. van Eijndhoven  Reconfigurable Processors and Applications of Embedded Systems 2006-IC-26
Vanne, Jarno
2006
Parallel Memory Implementation for Arbitrary Stride Accesses Eero Aho, Jarno Vanne, Timo D. Hämäläinen Embedded Processors and Architectures 2006-IC-01
Vassiliadis, Stamatis
2006
FLUX Networks: Interconnects on Demand Stamatis Vassiliadis, Ioannis Sourdis System and Network-on-Chip Platforms 2006-IC-23
Villa, Francisco J.
2006
On the Evaluation of Dense Chip-Multiprocessor Architectures Francisco J. Villa, Manuel E. Acacio, Jose M. Garcia Embedded Processors and Architectures 2006-IC-04
Villa, Oreste
2006
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa  System and Network-on-Chip Platforms 2006-IC-21
Wang, Shuai
2006
On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors Shuai Wang, Jie Hu, Sotirios G. Ziavras Embedded Processors and Architectures 2006-IC-03
Wen, Y.
2006
SimGate: Full-System, Cycle-Close Simulation of the Stargate Sensor Network Intermediate Node Y. Wen, S. Gurun, Chohan Navraj, R. Wolski, C. Krintz  High Level System Design and Simulation 2006-IC-19
Wild, Thomas
2006
Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf  System and Network-on-Chip Platforms 2006-IC-22
Wolski, R.
2006
SimGate: Full-System, Cycle-Close Simulation of the Stargate Sensor Network Intermediate Node Y. Wen, S. Gurun, Chohan Navraj, R. Wolski, C. Krintz  High Level System Design and Simulation 2006-IC-19
Ykman-Couvreur, Ch.
2006
Pareto-Based Application Specification for MP-SoC Customized Run-Time Management Ch. Ykman-Couvreur, V. Nollet, Théodore Marescaux, Erik Brockmeyer, Francky Catthoor, Henk Corporaal   Design Space Exploration (1) 2006-IC-12
Ziavras, Sotirios G.
2006
On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors Shuai Wang, Jie Hu, Sotirios G. Ziavras Embedded Processors and Architectures 2006-IC-03
Agarwal, Nainesh
2007
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction Nainesh Agarwal, Nikitas J. Dimopoulos Embedded Processors 2007-WS-31
Alho, Timo
2007
SensorOS: A New Operating System for Time Critical WSN Applications Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensors 2007-WS-44
Anderson, Willie
2007
Software Is the Answer But What Is the Question? Willie Anderson  SAMOS VII - Keynote 2007-WS-01
Ayguadé, Eduard
2007
A Streaming Machine Description and Programming Model Paul M. Carpenter, David Rodenas, Xavier Martorell, Alex Ramirez, Eduard Ayguadé  Scheduling & Programming Models 2007-WS-13
Baek, Seungjae
2007
Model and Validation of Block Cleaning Cost for Flash Memory Seungjae Baek, Jongmoo Choi, Donghee Lee, Sam H. Noh  VLSI Architectures 2007-WS-07
Batsuuri, Tseesuren
2007
Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC Tseesuren Batsuuri, Je-Hoon Lee, Kyoung-Rok Cho SoC for SDR 2007-WS-38
Benjamin, Michael G.
2007
Stream Image Processing on a Dual-Core Embedded System Michael G. Benjamin, David Kaeli Multi-processor Architectures 2007-WS-17
Berekovi?, Mladen
2007
Design of 100 μW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovi?, Qin Zhao, Frank Bouwens, Jef Van Meerbergen   Wireless Sensors 2007-WS-40
Bernard, Thomas A. M.
2007
Strategies for Compiling μ TC to Novel Chip Multiprocessors Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg Multi-processor Architectures 2007-WS-15
Bertels, Koen
2007
A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis Embedded Processors 2007-WS-30
Biest, Alexis Vander
2007
A Framework Introducing Model Reversibility in SoC Design Space Exploration Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, Frederic Robert  Design Space Exploration 2007-WS-23
Bonzini, Paolo
2007
A Study of Energy Saving in Customizable Processors Paolo Bonzini, Dilek Harmanci, Laura Pozzi Embedded Processors 2007-WS-32
Boubekeur, Menouer
2007
SC2SCFL: Automated SystemC to SystemCFL  Translation Ka Lok Man, Andrea Fedeli, Michele Mercaldi, Menouer Boubekeur, Michel Schellekens  System Modeling and Simulation 2007-WS-06
Bougard, Bruno
2007
Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor   SoC for SDR 2007-WS-34
Bouwens, Frank
2007
Design of 100 μW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovi?, Qin Zhao, Frank Bouwens, Jef Van Meerbergen   Wireless Sensors 2007-WS-40
Calderón, Humberto
2007
High-Bandwidth Address Generation Unit Humberto Calderón, Carlo Galuzzi, Georgi N. Gaydadjiev, Stamatis Vassiliadis  Processor Components 2007-WS-27
Carlomagno Filho, José O.
2007
An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code José O. Carlomagno Filho, Luiz F. P. Santos, Luiz C. V. dos Santos Scheduling & Programming Models 2007-WS-11
Carpenter, Paul M.
2007
A Streaming Machine Description and Programming Model Paul M. Carpenter, David Rodenas, Xavier Martorell, Alex Ramirez, Eduard Ayguadé  Scheduling & Programming Models 2007-WS-13
Carvalho, Felipe G.
2007
A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems Max R. Schultz, Alexandre K. I. Mendonça, Felipe G. Carvalho, Olinto J. V. Furtado, Luiz C. V. Santos  System Modeling and Simulation 2007-WS-04
Catthoor, Francky
2007
Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor   SoC for SDR 2007-WS-34
Chakrabarti, Chaitali
2007
The Next Generation Challenge for Software Defined Radio Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztián Flautner  SoC for SDR 2007-WS-36
Chen, Chao
2007
VLSI Architecture for MRF Based Stereo Matching Sungchan Park, Chao Chen, Hong Jeong VLSI Architectures 2007-WS-08
Cho, Kyoung-Rok
2007
On-Chip Bus Modeling for Power and Performance Estimation Je-Hoon Lee, Young-Shin Cho, Seok-Man Kim, Kyoung-Rok Cho  Design Space Exploration 2007-WS-22
Cho, Kyoung-Rok
2007
Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC Tseesuren Batsuuri, Je-Hoon Lee, Kyoung-Rok Cho SoC for SDR 2007-WS-38
Cho, Young-Shin
2007
On-Chip Bus Modeling for Power and Performance Estimation Je-Hoon Lee, Young-Shin Cho, Seok-Man Kim, Kyoung-Rok Cho  Design Space Exploration 2007-WS-22
Choi, Jongmoo
2007
Model and Validation of Block Cleaning Cost for Flash Memory Seungjae Baek, Jongmoo Choi, Donghee Lee, Sam H. Noh  VLSI Architectures 2007-WS-07
Christiaens, Mark
2007
FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder Hendrik Eeckhaut, Harald Devos, Philippe Faes, Mark Christiaens, Dirk Stroobandt  Reconfigurable Architectures 2007-WS-19
Corsonello, Pasquale
2007
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing Marco Lanuzza, Stefania Perri, Pasquale Corsonello Reconfigurable Architectures 2007-WS-18
de Langen, Pepijn
2007
Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors Pepijn de Langen, Ben Juurlink VLSI Architectures 2007-WS-10
De Nil, Michael
2007
Design of 100 μW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovi?, Qin Zhao, Frank Bouwens, Jef Van Meerbergen   Wireless Sensors 2007-WS-40
Devos, Harald
2007
FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder Hendrik Eeckhaut, Harald Devos, Philippe Faes, Mark Christiaens, Dirk Stroobandt  Reconfigurable Architectures 2007-WS-19
Dimopoulos, Nikitas J.
2007
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction Nainesh Agarwal, Nikitas J. Dimopoulos Embedded Processors 2007-WS-31
dos Santos, Luiz C. V.
2007
An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code José O. Carlomagno Filho, Luiz F. P. Santos, Luiz C. V. dos Santos Scheduling & Programming Models 2007-WS-11
Dragomirescu, Daniela
2007
System Architecture Modeling of an UWB Receiver for Wireless Sensor Network Aubin Lecointre, Daniela Dragomirescu, Robert Plana Wireless Sensors 2007-WS-42
Eeckhaut, Hendrik
2007
FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder Hendrik Eeckhaut, Harald Devos, Philippe Faes, Mark Christiaens, Dirk Stroobandt  Reconfigurable Architectures 2007-WS-19
Esser, Norbert
2007
Improving TriMedia Cache Performance by Profile Guided Code Reordering Norbert Esser, Renga Sundararajan, Joachim Trescher Scheduling & Programming Models 2007-WS-12
Faes, Philippe
2007
FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder Hendrik Eeckhaut, Harald Devos, Philippe Faes, Mark Christiaens, Dirk Stroobandt  Reconfigurable Architectures 2007-WS-19
Fedeli, Andrea
2007
SC2SCFL: Automated SystemC to SystemCFL  Translation Ka Lok Man, Andrea Fedeli, Michele Mercaldi, Menouer Boubekeur, Michel Schellekens  System Modeling and Simulation 2007-WS-06
Fettweis, Gerhard
2007
Mapping and Performance Evaluation for Heterogeneous MP-SoCs Via Packing Bastian Ristau, Gerhard Fettweis Multi-processor Architectures 2007-WS-14
Flatt, Holger
2007
A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch  Processor Components 2007-WS-26
Flautner, Krisztián
2007
The Next Generation Challenge for Software Defined Radio Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztián Flautner  SoC for SDR 2007-WS-36
Flügel, Sebastian
2007
A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch  Processor Components 2007-WS-26
Furtado, Olinto J. V.
2007
A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems Max R. Schultz, Alexandre K. I. Mendonça, Felipe G. Carvalho, Olinto J. V. Furtado, Luiz C. V. Santos  System Modeling and Simulation 2007-WS-04
Galuzzi, Carlo
2007
High-Bandwidth Address Generation Unit Humberto Calderón, Carlo Galuzzi, Georgi N. Gaydadjiev, Stamatis Vassiliadis  Processor Components 2007-WS-27
Galuzzi, Carlo
2007
A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis Embedded Processors 2007-WS-30
Gaydadjiev, Georgi N.
2007
High-Bandwidth Address Generation Unit Humberto Calderón, Carlo Galuzzi, Georgi N. Gaydadjiev, Stamatis Vassiliadis  Processor Components 2007-WS-27
Glossner, John
2007
Trends in Low Power Handset Software Defined Radio John Glossner, Daniel Iancu, Mayan Moudgill, Michael Schulte, Stamatis Vassiliadis  SoC for SDR 2007-WS-33
Gupta, Rajesh
2007
An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks Zhong-Yi Jin, Curt Schurgers, Rajesh Gupta Wireless Sensors 2007-WS-43
Guzma, Vladimír
2007
Resource Conflict Detection in Simulation of Function Unit Pipelines Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala Processor Components 2007-WS-25
Ha, Soonhoi
2007
Communication Architecture Simulation on the Virtual Synchronization Framework Taewook Oh, Youngmin Yi, Soonhoi Ha System Modeling and Simulation 2007-WS-03
Hämäläinen, Panu
2007
Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen Wireless Sensors 2007-WS-45
Hämäläinen, Timo D.
2007
Evaluating Large System-on-Chip on Multi-FPGA Platform Ari Kulmala, Erno Salminen, Timo D. Hämäläinen Reconfigurable Architectures 2007-WS-20
Hämäläinen, Timo D.
2007
Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network Mauri Kuorilehto, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensors 2007-WS-41
Hämäläinen, Timo D.
2007
SensorOS: A New Operating System for Time Critical WSN Applications Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensors 2007-WS-44
Hämäläinen, Timo D.
2007
Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen Wireless Sensors 2007-WS-45
Hännikäinen, Marko
2007
Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network Mauri Kuorilehto, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensors 2007-WS-41
Hännikäinen, Marko
2007
SensorOS: A New Operating System for Time Critical WSN Applications Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensors 2007-WS-44
Hännikäinen, Marko
2007
Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks Panu Hämäläinen, Marko Hännikäinen, Timo D. Hämäläinen Wireless Sensors 2007-WS-45
Harmanci, Dilek
2007
A Study of Energy Saving in Customizable Processors Paolo Bonzini, Dilek Harmanci, Laura Pozzi Embedded Processors 2007-WS-32
Hesselbarth, Sebastian
2007
A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch  Processor Components 2007-WS-26
Huisken, Jos
2007
Integrating VLIW Processors with a Network on Chip Jos Huisken  SAMOS VII - Keynote 2007-WS-02
Huisken, Jos
2007
Design of 100 μW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovi?, Qin Zhao, Frank Bouwens, Jef Van Meerbergen   Wireless Sensors 2007-WS-40
Iancu, Daniel
2007
Trends in Low Power Handset Software Defined Radio John Glossner, Daniel Iancu, Mayan Moudgill, Michael Schulte, Stamatis Vassiliadis  SoC for SDR 2007-WS-33
Jääskeläinen, Pekka
2007
Resource Conflict Detection in Simulation of Function Unit Pipelines Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala Processor Components 2007-WS-25
Jacobs, Jan W. M.
2007
Image Quantisation on a Massively Parallel Embedded Processor Jan W. M. Jacobs, Leroy van Engelen, Jan Kuper, Gerard J. M. Smit  Multi-processor Architectures 2007-WS-16
Jeong, Hong
2007
VLSI Architecture for MRF Based Stereo Matching Sungchan Park, Chao Chen, Hong Jeong VLSI Architectures 2007-WS-08
Jeschke, Hartwig
2007
Efficiency Measures for Multimedia SOCs Hartwig Jeschke  Design Space Exploration 2007-WS-21
Jesshope, Chris R.
2007
Strategies for Compiling μ TC to Novel Chip Multiprocessors Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg Multi-processor Architectures 2007-WS-15
Jin, Zhong-Yi
2007
An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks Zhong-Yi Jin, Curt Schurgers, Rajesh Gupta Wireless Sensors 2007-WS-43
Juurlink, Ben
2007
Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors Pepijn de Langen, Ben Juurlink VLSI Architectures 2007-WS-10
Kaeli, David
2007
Stream Image Processing on a Dual-Core Embedded System Michael G. Benjamin, David Kaeli Multi-processor Architectures 2007-WS-17
Khan, Md. Zafar Ali
2007
A Comparative Study of Different FFT Architectures for Software Defined Radio Shashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas SoC for SDR 2007-WS-39
Kim, Seok-Man
2007
On-Chip Bus Modeling for Power and Performance Estimation Je-Hoon Lee, Young-Shin Cho, Seok-Man Kim, Kyoung-Rok Cho  Design Space Exploration 2007-WS-22
Knijnenburg, Peter M. W.
2007
Strategies for Compiling μ TC to Novel Chip Multiprocessors Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg Multi-processor Architectures 2007-WS-15
Ko, Young-Bae
2007
k+ Neigh: An Energy Efficient Topology Control for Wireless Sensor Networks Dong-Min Son, Young-Bae Ko Wireless Sensors 2007-WS-46
Kulmala, Ari
2007
Evaluating Large System-on-Chip on Multi-FPGA Platform Ari Kulmala, Erno Salminen, Timo D. Hämäläinen Reconfigurable Architectures 2007-WS-20
Kuorilehto, Mauri
2007
Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network Mauri Kuorilehto, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensors 2007-WS-41
Kuorilehto, Mauri
2007
SensorOS: A New Operating System for Time Critical WSN Applications Mauri Kuorilehto, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensors 2007-WS-44
Kuper, Jan
2007
Image Quantisation on a Massively Parallel Embedded Processor Jan W. M. Jacobs, Leroy van Engelen, Jan Kuper, Gerard J. M. Smit  Multi-processor Architectures 2007-WS-16
Lanuzza, Marco
2007
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing Marco Lanuzza, Stefania Perri, Pasquale Corsonello Reconfigurable Architectures 2007-WS-18
Lecointre, Aubin
2007
System Architecture Modeling of an UWB Receiver for Wireless Sensor Network Aubin Lecointre, Daniela Dragomirescu, Robert Plana Wireless Sensors 2007-WS-42
Lee, Chia-han
2007
Design Methodology for Software Radio Systems Chia-han Lee, Wayne Wolf SoC for SDR 2007-WS-37
Lee, Donghee
2007
Model and Validation of Block Cleaning Cost for Flash Memory Seungjae Baek, Jongmoo Choi, Donghee Lee, Sam H. Noh  VLSI Architectures 2007-WS-07
Lee, Hyunseok
2007
The Next Generation Challenge for Software Defined Radio Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztián Flautner  SoC for SDR 2007-WS-36
Lee, Je-Hoon
2007
On-Chip Bus Modeling for Power and Performance Estimation Je-Hoon Lee, Young-Shin Cho, Seok-Man Kim, Kyoung-Rok Cho  Design Space Exploration 2007-WS-22
Lee, Je-Hoon
2007
Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC Tseesuren Batsuuri, Je-Hoon Lee, Kyoung-Rok Cho SoC for SDR 2007-WS-38
Lin, Yuan
2007
The Next Generation Challenge for Software Defined Radio Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztián Flautner  SoC for SDR 2007-WS-36
Liu, Dake
2007
Area Efficient Fully Programmable Baseband Processors Anders Nilsson, Dake Liu SoC for SDR 2007-WS-35
Mahlke, Scott
2007
The Next Generation Challenge for Software Defined Radio Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztián Flautner  SoC for SDR 2007-WS-36
Mäkinen, Risto
2007
Parallel Memory Architecture for TTA Processor Jarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala  Embedded Processors 2007-WS-29
Man, Ka Lok
2007
SC2SCFL: Automated SystemC to SystemCFL  Translation Ka Lok Man, Andrea Fedeli, Michele Mercaldi, Menouer Boubekeur, Michel Schellekens  System Modeling and Simulation 2007-WS-06
Martorell, Xavier
2007
A Streaming Machine Description and Programming Model Paul M. Carpenter, David Rodenas, Xavier Martorell, Alex Ramirez, Eduard Ayguadé  Scheduling & Programming Models 2007-WS-13
Mendonça, Alexandre K. I.
2007
A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems Max R. Schultz, Alexandre K. I. Mendonça, Felipe G. Carvalho, Olinto J. V. Furtado, Luiz C. V. Santos  System Modeling and Simulation 2007-WS-04
Mercaldi, Michele
2007
SC2SCFL: Automated SystemC to SystemCFL  Translation Ka Lok Man, Andrea Fedeli, Michele Mercaldi, Menouer Boubekeur, Michel Schellekens  System Modeling and Simulation 2007-WS-06
Milojevic, Dragomir
2007
A Framework Introducing Model Reversibility in SoC Design Space Exploration Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, Frederic Robert  Design Space Exploration 2007-WS-23
Mische, Jörg
2007
An IP Core for Embedded Java Systems Sascha Uhrig, Jörg Mische, Theo Ungerer Processor Components 2007-WS-28
Mittal, Shashank
2007
A Comparative Study of Different FFT Architectures for Software Defined Radio Shashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas SoC for SDR 2007-WS-39
Moudgill, Mayan
2007
Trends in Low Power Handset Software Defined Radio John Glossner, Daniel Iancu, Mayan Moudgill, Michael Schulte, Stamatis Vassiliadis  SoC for SDR 2007-WS-33
Mudge, Trevor
2007
The Next Generation Challenge for Software Defined Radio Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztián Flautner  SoC for SDR 2007-WS-36
Nilsson, Anders
2007
Area Efficient Fully Programmable Baseband Processors Anders Nilsson, Dake Liu SoC for SDR 2007-WS-35
Noh, Sam H.
2007
Model and Validation of Block Cleaning Cost for Flash Memory Seungjae Baek, Jongmoo Choi, Donghee Lee, Sam H. Noh  VLSI Architectures 2007-WS-07
Novo, David
2007
Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor   SoC for SDR 2007-WS-34
Oh, Taewook
2007
Communication Architecture Simulation on the Virtual Synchronization Framework Taewook Oh, Youngmin Yi, Soonhoi Ha System Modeling and Simulation 2007-WS-03
Park, Sangsoo
2007
Performance Evaluation of Memory Management Configurations in Linux for an OS-Level Design Space Exploration Sangsoo Park, Heonshik Shin System Modeling and Simulation 2007-WS-05
Park, Sungchan
2007
VLSI Architecture for MRF Based Stereo Matching Sungchan Park, Chao Chen, Hong Jeong VLSI Architectures 2007-WS-08
Partanen, Tero
2007
Low-Power Twiddle Factor Unit for FFT Computation Teemu Pitkänen, Tero Partanen, Jarmo Takala VLSI Architectures 2007-WS-09
Perri, Stefania
2007
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing Marco Lanuzza, Stefania Perri, Pasquale Corsonello Reconfigurable Architectures 2007-WS-18
Pimentel, Andy D.
2007
Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration Mark Thompson, Andy D. Pimentel Design Space Exploration 2007-WS-24
Pirsch, Peter
2007
A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch  Processor Components 2007-WS-26
Pitkänen, Teemu
2007
Parallel Memory Architecture for TTA Processor Jarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala  Embedded Processors 2007-WS-29
Pitkänen, Teemu
2007
Low-Power Twiddle Factor Unit for FFT Computation Teemu Pitkänen, Tero Partanen, Jarmo Takala VLSI Architectures 2007-WS-09
Plana, Robert
2007
System Architecture Modeling of an UWB Receiver for Wireless Sensor Network Aubin Lecointre, Daniela Dragomirescu, Robert Plana Wireless Sensors 2007-WS-42
Pozzi, Laura
2007
A Study of Energy Saving in Customizable Processors Paolo Bonzini, Dilek Harmanci, Laura Pozzi Embedded Processors 2007-WS-32
Priewasser, Robert
2007
Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor   SoC for SDR 2007-WS-34
Raghavan, Praveen
2007
Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor   SoC for SDR 2007-WS-34
Ramirez, Alex
2007
A Streaming Machine Description and Programming Model Paul M. Carpenter, David Rodenas, Xavier Martorell, Alex Ramirez, Eduard Ayguadé  Scheduling & Programming Models 2007-WS-13
Richard, Alienor
2007
A Framework Introducing Model Reversibility in SoC Design Space Exploration Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, Frederic Robert  Design Space Exploration 2007-WS-23
Ristau, Bastian
2007
Mapping and Performance Evaluation for Heterogeneous MP-SoCs Via Packing Bastian Ristau, Gerhard Fettweis Multi-processor Architectures 2007-WS-14
Robert, Frederic
2007
A Framework Introducing Model Reversibility in SoC Design Space Exploration Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, Frederic Robert  Design Space Exploration 2007-WS-23
Rodenas, David
2007
A Streaming Machine Description and Programming Model Paul M. Carpenter, David Rodenas, Xavier Martorell, Alex Ramirez, Eduard Ayguadé  Scheduling & Programming Models 2007-WS-13
Salminen, Erno
2007
Evaluating Large System-on-Chip on Multi-FPGA Platform Ari Kulmala, Erno Salminen, Timo D. Hämäläinen Reconfigurable Architectures 2007-WS-20
Santos, Luiz C. V.
2007
A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems Max R. Schultz, Alexandre K. I. Mendonça, Felipe G. Carvalho, Olinto J. V. Furtado, Luiz C. V. Santos  System Modeling and Simulation 2007-WS-04
Santos, Luiz F. P.
2007
An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code José O. Carlomagno Filho, Luiz F. P. Santos, Luiz C. V. dos Santos Scheduling & Programming Models 2007-WS-11
Schellekens, Michel
2007
SC2SCFL: Automated SystemC to SystemCFL  Translation Ka Lok Man, Andrea Fedeli, Michele Mercaldi, Menouer Boubekeur, Michel Schellekens  System Modeling and Simulation 2007-WS-06
Schulte, Michael
2007
Trends in Low Power Handset Software Defined Radio John Glossner, Daniel Iancu, Mayan Moudgill, Michael Schulte, Stamatis Vassiliadis  SoC for SDR 2007-WS-33
Schultz, Max R.
2007
A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems Max R. Schultz, Alexandre K. I. Mendonça, Felipe G. Carvalho, Olinto J. V. Furtado, Luiz C. V. Santos  System Modeling and Simulation 2007-WS-04
Schurgers, Curt
2007
An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks Zhong-Yi Jin, Curt Schurgers, Rajesh Gupta Wireless Sensors 2007-WS-43
Schuster, Thomas
2007
Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor   SoC for SDR 2007-WS-34
Seo, Sangwon
2007
The Next Generation Challenge for Software Defined Radio Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztián Flautner  SoC for SDR 2007-WS-36
Shin, Heonshik
2007
Performance Evaluation of Memory Management Configurations in Linux for an OS-Level Design Space Exploration Sangsoo Park, Heonshik Shin System Modeling and Simulation 2007-WS-05
Smit, Gerard J. M.
2007
Image Quantisation on a Massively Parallel Embedded Processor Jan W. M. Jacobs, Leroy van Engelen, Jan Kuper, Gerard J. M. Smit  Multi-processor Architectures 2007-WS-16
Son, Dong-Min
2007
k+ Neigh: An Energy Efficient Topology Control for Wireless Sensor Networks Dong-Min Son, Young-Bae Ko Wireless Sensors 2007-WS-46
Srinivas, M. B.
2007
A Comparative Study of Different FFT Architectures for Software Defined Radio Shashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas SoC for SDR 2007-WS-39
Stroobandt, Dirk
2007
FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder Hendrik Eeckhaut, Harald Devos, Philippe Faes, Mark Christiaens, Dirk Stroobandt  Reconfigurable Architectures 2007-WS-19
Suhonen, Jukka
2007
Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network Mauri Kuorilehto, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen  Wireless Sensors 2007-WS-41
Sundararajan, Renga
2007
Improving TriMedia Cache Performance by Profile Guided Code Reordering Norbert Esser, Renga Sundararajan, Joachim Trescher Scheduling & Programming Models 2007-WS-12
Takala, Jarmo
2007
Resource Conflict Detection in Simulation of Function Unit Pipelines Pekka Jääskeläinen, Vladimír Guzma, Jarmo Takala Processor Components 2007-WS-25
Takala, Jarmo
2007
Parallel Memory Architecture for TTA Processor Jarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala  Embedded Processors 2007-WS-29
Takala, Jarmo
2007
Low-Power Twiddle Factor Unit for FFT Computation Teemu Pitkänen, Tero Partanen, Jarmo Takala VLSI Architectures 2007-WS-09
Tanskanen, Jarno K.
2007
Parallel Memory Architecture for TTA Processor Jarno K. Tanskanen, Teemu Pitkänen, Risto Mäkinen, Jarmo Takala  Embedded Processors 2007-WS-29
Thompson, Mark
2007
Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration Mark Thompson, Andy D. Pimentel Design Space Exploration 2007-WS-24
Trescher, Joachim
2007
Improving TriMedia Cache Performance by Profile Guided Code Reordering Norbert Esser, Renga Sundararajan, Joachim Trescher Scheduling & Programming Models 2007-WS-12
Uhrig, Sascha
2007
An IP Core for Embedded Java Systems Sascha Uhrig, Jörg Mische, Theo Ungerer Processor Components 2007-WS-28
Ungerer, Theo
2007
An IP Core for Embedded Java Systems Sascha Uhrig, Jörg Mische, Theo Ungerer Processor Components 2007-WS-28
Van der Perre, Liesbet
2007
Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals Thomas Schuster, Bruno Bougard, Praveen Raghavan, Robert Priewasser, David Novo, Liesbet Van der Perre, Francky Catthoor   SoC for SDR 2007-WS-34
van Engelen, Leroy
2007
Image Quantisation on a Massively Parallel Embedded Processor Jan W. M. Jacobs, Leroy van Engelen, Jan Kuper, Gerard J. M. Smit  Multi-processor Architectures 2007-WS-16
Van Meerbergen, Jef
2007
Design of 100 μW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovi?, Qin Zhao, Frank Bouwens, Jef Van Meerbergen   Wireless Sensors 2007-WS-40
Vassiliadis, Stamatis
2007
High-Bandwidth Address Generation Unit Humberto Calderón, Carlo Galuzzi, Georgi N. Gaydadjiev, Stamatis Vassiliadis  Processor Components 2007-WS-27
Vassiliadis, Stamatis
2007
A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis Embedded Processors 2007-WS-30
Vassiliadis, Stamatis
2007
Trends in Low Power Handset Software Defined Radio John Glossner, Daniel Iancu, Mayan Moudgill, Michael Schulte, Stamatis Vassiliadis  SoC for SDR 2007-WS-33
Woh, Mark
2007
The Next Generation Challenge for Software Defined Radio Mark Woh, Sangwon Seo, Hyunseok Lee, Yuan Lin, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti, Krisztián Flautner  SoC for SDR 2007-WS-36
Wolf, Wayne
2007
Design Methodology for Software Radio Systems Chia-han Lee, Wayne Wolf SoC for SDR 2007-WS-37
Yi, Youngmin
2007
Communication Architecture Simulation on the Virtual Synchronization Framework Taewook Oh, Youngmin Yi, Soonhoi Ha System Modeling and Simulation 2007-WS-03
Yseboodt, Lennart
2007
Design of 100 μW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovi?, Qin Zhao, Frank Bouwens, Jef Van Meerbergen   Wireless Sensors 2007-WS-40
Zhao, Qin
2007
Design of 100 μW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovi?, Qin Zhao, Frank Bouwens, Jef Van Meerbergen   Wireless Sensors 2007-WS-40
Badel, S.
2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies F. Regazzoni, S. Badel, T. Eisenbarth, Johann Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, Laura Pozzi, C. Paar, Y.  Leblebici, Paolo Ienne  Cryptography 2007-IC-27
Baloukas, C.
2007
Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems L. Papadopoulos, C. Baloukas, N. Zompakis, Dimitrios Soudris  Design Space Exploration 2007-IC-08
Batina, L.
2007
A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications N. Mentens, K. Sakiyama, L. Batina, B. Preneel, I. Verbauwhede  Cryptography 2007-IC-25
Benoit, Pascal
2007
Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems N. Saint-Jean, Pascal Benoit, Gilles Sassatelli, L. Torres, Michel Robert  Multiprocessor Architectures 2007-IC-12
Bjork, M.
2007
FlexCore: Utilizing Exposed Datapath Control for Effcient Computing  M. Thuresson, M. Sjalander, M. Bjork, L. Svensson, P. Larsson-Edefors, Per Stenstrom   Processor Architectures 2007-IC-03
Blume, Holger
2007
Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform Holger Blume, J.v. Livonius, L. Rotenberg, Tobias G. Noll, H. Bothe, Jörg Brakensiek   Multiprocessor Architectures 2007-IC-10
Borodin, Demid
2007
Instruction-Level Fault Tolerance Configurability Demid Borodin, Ben Juurlink, Stamatis Vassiliadis Systems and Applications 2007-IC-15
Bothe, H.
2007
Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform Holger Blume, J.v. Livonius, L. Rotenberg, Tobias G. Noll, H. Bothe, Jörg Brakensiek   Multiprocessor Architectures 2007-IC-10
Brakensiek, Jörg
2007
Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform Holger Blume, J.v. Livonius, L. Rotenberg, Tobias G. Noll, H. Bothe, Jörg Brakensiek   Multiprocessor Architectures 2007-IC-10
Branca, M.
2007
An Interrupt Controller for FPGA-based Multiprocessors  Antonino Tumeo, M. Branca, L. Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto   Multiprocessor Architectures 2007-IC-11
Camerini, L.
2007
An Interrupt Controller for FPGA-based Multiprocessors  Antonino Tumeo, M. Branca, L. Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto   Multiprocessor Architectures 2007-IC-11
Cazorla, F.J.
2007
On the Problem of Minimizing Workload Execution Time in SMT processors F.J. Cazorla, Peter M. W. Knijnenburg, R. Sakellariou, E. Fernandez, Alex Ramirez, Mateo Valero   Multiprocessor Architectures 2007-IC-09
Cazorla, F.J.
2007
Online Prediction of Applications Cache Utility M. Moreto, F.J. Cazorla, Alex Ramirez, Mateo Valero  Memory Architectures and Memory Optimization 2007-IC-22
Cuenca, S.
2007
A Hardware/Software Architecture for Tool Path Computation. An Application to Turning Lathe Machining S. Cuenca, A. Martinez, A. Jimeno, J.L. Sanchez  Systems and Applications 2007-IC-13
Dimopoulos, V.
2007
A Memory-Effcient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems V. Dimopoulos, I. Papaefstathiou, D. Pnevmatikatos Memory Architectures and Memory Optimization 2007-IC-24
Economakos, George
2007
Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme S. Xydis, George Economakos, Kiamal Pekmestzi Reconfigurable Architectures 2007-IC-18
Eisenbarth, T.
2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies F. Regazzoni, S. Badel, T. Eisenbarth, Johann Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, Laura Pozzi, C. Paar, Y.  Leblebici, Paolo Ienne  Cryptography 2007-IC-27
Fernandez, E.
2007
On the Problem of Minimizing Workload Execution Time in SMT processors F.J. Cazorla, Peter M. W. Knijnenburg, R. Sakellariou, E. Fernandez, Alex Ramirez, Mateo Valero   Multiprocessor Architectures 2007-IC-09
Ferrandi, Fabrizio
2007
An Interrupt Controller for FPGA-based Multiprocessors  Antonino Tumeo, M. Branca, L. Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto   Multiprocessor Architectures 2007-IC-11
Ferrandi, Fabrizio
2007
An Evolutionary Approach to Area-Time Optimization of FPGA designs Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo   Reconfigurable Architectures 2007-IC-19
Ganghee, Lee
2007
Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration Lee Ganghee, Lee Seokhyun, Ahn Yongjin, Choi Kiyoung  Design Space Exploration 2007-IC-07
Garbinato, B.
2007
The Weight-Watcher Service and its Lightweight Implementation B. Garbinato, R. Guerraoui, J. Hulaas, A. Kounine, M. Monod, J.H. Spring   Systems and Applications 2007-IC-16
Großschädl, Johann
2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies F. Regazzoni, S. Badel, T. Eisenbarth, Johann Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, Laura Pozzi, C. Paar, Y.  Leblebici, Paolo Ienne  Cryptography 2007-IC-27
Guerraoui, R.
2007
The Weight-Watcher Service and its Lightweight Implementation B. Garbinato, R. Guerraoui, J. Hulaas, A. Kounine, M. Monod, J.H. Spring   Systems and Applications 2007-IC-16
Haubelt, Christian
2007
Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow  J. Keinert, Christian Haubelt, Jürgen Teich Memory Architectures and Memory Optimization 2007-IC-21
Herruzo, E.
2007
Maximum and Sorted Cache Occupation Using Array Padding  E. Herruzo, E.L. Zapata, O. Plata Memory Architectures and Memory Optimization 2007-IC-23
Hulaas, J.
2007
The Weight-Watcher Service and its Lightweight Implementation B. Garbinato, R. Guerraoui, J. Hulaas, A. Kounine, M. Monod, J.H. Spring   Systems and Applications 2007-IC-16
Ienne, Paolo
2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies F. Regazzoni, S. Badel, T. Eisenbarth, Johann Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, Laura Pozzi, C. Paar, Y.  Leblebici, Paolo Ienne  Cryptography 2007-IC-27
Ioannou, A.
2007
Prototyping Effcient Interprocessor Communication Mechanisms  V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, Manolis G.H. Katevenis  Processor Architectures 2007-IC-04
Jimeno, A.
2007
A Hardware/Software Architecture for Tool Path Computation. An Application to Turning Lathe Machining S. Cuenca, A. Martinez, A. Jimeno, J.L. Sanchez  Systems and Applications 2007-IC-13
Juurlink, Ben
2007
Instruction-Level Fault Tolerance Configurability Demid Borodin, Ben Juurlink, Stamatis Vassiliadis Systems and Applications 2007-IC-15
Kachris, Christoforos
2007
Design Space Exploration of Configuration Manager for Network Processing Applications Christoforos Kachris, Stamatis Vassiliadis Design Space Exploration 2007-IC-05
Kalokairinos, G.
2007
Prototyping Effcient Interprocessor Communication Mechanisms  V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, Manolis G.H. Katevenis  Processor Architectures 2007-IC-04
Katevenis, Manolis G.H.
2007
Prototyping Effcient Interprocessor Communication Mechanisms  V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, Manolis G.H. Katevenis  Processor Architectures 2007-IC-04
Kaufmann, A.
2007
Applying Data Mapping Techniques to Vector DSPs Peter Westermann, L. Schwoerer, A. Kaufmann Processor Architectures 2007-IC-01
Kavadias, S.
2007
Prototyping Effcient Interprocessor Communication Mechanisms  V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, Manolis G.H. Katevenis  Processor Architectures 2007-IC-04
Kehuai, Wu
2007
COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable Systems Wu Kehuai, J. Madsen Reconfigurable Architectures 2007-IC-17
Keinert, J.
2007
Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow  J. Keinert, Christian Haubelt, Jürgen Teich Memory Architectures and Memory Optimization 2007-IC-21
Kiyoung, Choi
2007
Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration Lee Ganghee, Lee Seokhyun, Ahn Yongjin, Choi Kiyoung  Design Space Exploration 2007-IC-07
Knijnenburg, Peter M. W.
2007
On the Problem of Minimizing Workload Execution Time in SMT processors F.J. Cazorla, Peter M. W. Knijnenburg, R. Sakellariou, E. Fernandez, Alex Ramirez, Mateo Valero   Multiprocessor Architectures 2007-IC-09
Kounine, A.
2007
The Weight-Watcher Service and its Lightweight Implementation B. Garbinato, R. Guerraoui, J. Hulaas, A. Kounine, M. Monod, J.H. Spring   Systems and Applications 2007-IC-16
Krall, A.
2007
Instruction Set Encoding Optimization for Code Size Reduction  M. Med, A. Krall Processor Architectures 2007-IC-02
Lanzi, Pier Luca
2007
An Evolutionary Approach to Area-Time Optimization of FPGA designs Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo   Reconfigurable Architectures 2007-IC-19
Larsson-Edefors, P.
2007
FlexCore: Utilizing Exposed Datapath Control for Effcient Computing  M. Thuresson, M. Sjalander, M. Bjork, L. Svensson, P. Larsson-Edefors, Per Stenstrom   Processor Architectures 2007-IC-03
Leblebici, Y.
2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies F. Regazzoni, S. Badel, T. Eisenbarth, Johann Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, Laura Pozzi, C. Paar, Y.  Leblebici, Paolo Ienne  Cryptography 2007-IC-27
Livonius, J.v.
2007
Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform Holger Blume, J.v. Livonius, L. Rotenberg, Tobias G. Noll, H. Bothe, Jörg Brakensiek   Multiprocessor Architectures 2007-IC-10
Macchetti, M.
2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies F. Regazzoni, S. Badel, T. Eisenbarth, Johann Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, Laura Pozzi, C. Paar, Y.  Leblebici, Paolo Ienne  Cryptography 2007-IC-27
Madsen, J.
2007
COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable Systems Wu Kehuai, J. Madsen Reconfigurable Architectures 2007-IC-17
Marazakis, M.
2007
Prototyping Effcient Interprocessor Communication Mechanisms  V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, Manolis G.H. Katevenis  Processor Architectures 2007-IC-04
Martin-Langerwerf, J.
2007
Design Space Exploration of Media Processors: A Parameterized Scheduler Guillermo Payá Vayá, J. Martin-Langerwerf, P. Taptimthong, Peter Pirsch  Design Space Exploration 2007-IC-06
Martinez, A.
2007
A Hardware/Software Architecture for Tool Path Computation. An Application to Turning Lathe Machining S. Cuenca, A. Martinez, A. Jimeno, J.L. Sanchez  Systems and Applications 2007-IC-13
Med, M.
2007
Instruction Set Encoding Optimization for Code Size Reduction  M. Med, A. Krall Processor Architectures 2007-IC-02
Mentens, N.
2007
A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications N. Mentens, K. Sakiyama, L. Batina, B. Preneel, I. Verbauwhede  Cryptography 2007-IC-25
Mihelogiannakis, G.
2007
Prototyping Effcient Interprocessor Communication Mechanisms  V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, Manolis G.H. Katevenis  Processor Architectures 2007-IC-04
Monchiero, Matteo
2007
An Interrupt Controller for FPGA-based Multiprocessors  Antonino Tumeo, M. Branca, L. Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto   Multiprocessor Architectures 2007-IC-11
Monod, M.
2007
The Weight-Watcher Service and its Lightweight Implementation B. Garbinato, R. Guerraoui, J. Hulaas, A. Kounine, M. Monod, J.H. Spring   Systems and Applications 2007-IC-16
Moreto, M.
2007
Online Prediction of Applications Cache Utility M. Moreto, F.J. Cazorla, Alex Ramirez, Mateo Valero  Memory Architectures and Memory Optimization 2007-IC-22
Muhlbach, S.
2007
Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity Machines S. Muhlbach, S. Wallner Cryptography 2007-IC-26
Nikolaidis, S.
2007
The ARISE Reconfigurable Instruction Set Extensions Framework N. Vassiliadis, G. Theodoridis, S. Nikolaidis Reconfigurable Architectures 2007-IC-20
Noll, Tobias G.
2007
Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform Holger Blume, J.v. Livonius, L. Rotenberg, Tobias G. Noll, H. Bothe, Jörg Brakensiek   Multiprocessor Architectures 2007-IC-10
Paar, C.
2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies F. Regazzoni, S. Badel, T. Eisenbarth, Johann Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, Laura Pozzi, C. Paar, Y.  Leblebici, Paolo Ienne  Cryptography 2007-IC-27
Palermo, Gianluca
2007
An Interrupt Controller for FPGA-based Multiprocessors  Antonino Tumeo, M. Branca, L. Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto   Multiprocessor Architectures 2007-IC-11
Palermo, Gianluca
2007
An Evolutionary Approach to Area-Time Optimization of FPGA designs Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo   Reconfigurable Architectures 2007-IC-19
Papadopoulos, L.
2007
Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems L. Papadopoulos, C. Baloukas, N. Zompakis, Dimitrios Soudris  Design Space Exploration 2007-IC-08
Papaefstathiou, I.
2007
A Memory-Effcient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems V. Dimopoulos, I. Papaefstathiou, D. Pnevmatikatos Memory Architectures and Memory Optimization 2007-IC-24
Papaefstathiou, V.
2007
Prototyping Effcient Interprocessor Communication Mechanisms  V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, Manolis G.H. Katevenis  Processor Architectures 2007-IC-04
Papamichael, M.
2007
Prototyping Effcient Interprocessor Communication Mechanisms  V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, Manolis G.H. Katevenis  Processor Architectures 2007-IC-04
Payá Vayá, Guillermo
2007
Design Space Exploration of Media Processors: A Parameterized Scheduler Guillermo Payá Vayá, J. Martin-Langerwerf, P. Taptimthong, Peter Pirsch  Design Space Exploration 2007-IC-06
Pekmestzi, Kiamal
2007
Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme S. Xydis, George Economakos, Kiamal Pekmestzi Reconfigurable Architectures 2007-IC-18
Pilato, Christian
2007
An Evolutionary Approach to Area-Time Optimization of FPGA designs Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo   Reconfigurable Architectures 2007-IC-19
Pirsch, Peter
2007
Design Space Exploration of Media Processors: A Parameterized Scheduler Guillermo Payá Vayá, J. Martin-Langerwerf, P. Taptimthong, Peter Pirsch  Design Space Exploration 2007-IC-06
Plata, O.
2007
Maximum and Sorted Cache Occupation Using Array Padding  E. Herruzo, E.L. Zapata, O. Plata Memory Architectures and Memory Optimization 2007-IC-23
Pnevmatikatos, D.
2007
Prototyping Effcient Interprocessor Communication Mechanisms  V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, Manolis G.H. Katevenis  Processor Architectures 2007-IC-04
Pnevmatikatos, D.
2007
A Memory-Effcient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems V. Dimopoulos, I. Papaefstathiou, D. Pnevmatikatos Memory Architectures and Memory Optimization 2007-IC-24
Poschmann, A.
2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies F. Regazzoni, S. Badel, T. Eisenbarth, Johann Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, Laura Pozzi, C. Paar, Y.  Leblebici, Paolo Ienne  Cryptography 2007-IC-27
Pozzi, Laura
2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies F. Regazzoni, S. Badel, T. Eisenbarth, Johann Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, Laura Pozzi, C. Paar, Y.  Leblebici, Paolo Ienne  Cryptography 2007-IC-27
Preneel, B.
2007
A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications N. Mentens, K. Sakiyama, L. Batina, B. Preneel, I. Verbauwhede  Cryptography 2007-IC-25
Ramirez, Alex
2007
On the Problem of Minimizing Workload Execution Time in SMT processors F.J. Cazorla, Peter M. W. Knijnenburg, R. Sakellariou, E. Fernandez, Alex Ramirez, Mateo Valero   Multiprocessor Architectures 2007-IC-09
Ramirez, Alex
2007
Online Prediction of Applications Cache Utility M. Moreto, F.J. Cazorla, Alex Ramirez, Mateo Valero  Memory Architectures and Memory Optimization 2007-IC-22
Regazzoni, F.
2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies F. Regazzoni, S. Badel, T. Eisenbarth, Johann Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, Laura Pozzi, C. Paar, Y.  Leblebici, Paolo Ienne  Cryptography 2007-IC-27
Rintaluoma, Tero
2007
Energy effciency of mobile video decoding Tero Rintaluoma, Olli Silven Systems and Applications 2007-IC-14
Robert, Michel
2007
Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems N. Saint-Jean, Pascal Benoit, Gilles Sassatelli, L. Torres, Michel Robert  Multiprocessor Architectures 2007-IC-12
Rotenberg, L.
2007
Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform Holger Blume, J.v. Livonius, L. Rotenberg, Tobias G. Noll, H. Bothe, Jörg Brakensiek   Multiprocessor Architectures 2007-IC-10
Saint-Jean, N.
2007
Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems N. Saint-Jean, Pascal Benoit, Gilles Sassatelli, L. Torres, Michel Robert  Multiprocessor Architectures 2007-IC-12
Sakellariou, R.
2007
On the Problem of Minimizing Workload Execution Time in SMT processors F.J. Cazorla, Peter M. W. Knijnenburg, R. Sakellariou, E. Fernandez, Alex Ramirez, Mateo Valero   Multiprocessor Architectures 2007-IC-09
Sakiyama, K.
2007
A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications N. Mentens, K. Sakiyama, L. Batina, B. Preneel, I. Verbauwhede  Cryptography 2007-IC-25
Sanchez, J.L.
2007
A Hardware/Software Architecture for Tool Path Computation. An Application to Turning Lathe Machining S. Cuenca, A. Martinez, A. Jimeno, J.L. Sanchez  Systems and Applications 2007-IC-13
Sassatelli, Gilles
2007
Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems N. Saint-Jean, Pascal Benoit, Gilles Sassatelli, L. Torres, Michel Robert  Multiprocessor Architectures 2007-IC-12
Schwoerer, L.
2007
Applying Data Mapping Techniques to Vector DSPs Peter Westermann, L. Schwoerer, A. Kaufmann Processor Architectures 2007-IC-01
Sciuto, Donatella
2007
An Interrupt Controller for FPGA-based Multiprocessors  Antonino Tumeo, M. Branca, L. Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto   Multiprocessor Architectures 2007-IC-11
Sciuto, Donatella
2007
An Evolutionary Approach to Area-Time Optimization of FPGA designs Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo   Reconfigurable Architectures 2007-IC-19
Seokhyun, Lee
2007
Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration Lee Ganghee, Lee Seokhyun, Ahn Yongjin, Choi Kiyoung  Design Space Exploration 2007-IC-07
Silven, Olli
2007
Energy effciency of mobile video decoding Tero Rintaluoma, Olli Silven Systems and Applications 2007-IC-14
Sjalander, M.
2007
FlexCore: Utilizing Exposed Datapath Control for Effcient Computing  M. Thuresson, M. Sjalander, M. Bjork, L. Svensson, P. Larsson-Edefors, Per Stenstrom   Processor Architectures 2007-IC-03
Soudris, Dimitrios
2007
Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems L. Papadopoulos, C. Baloukas, N. Zompakis, Dimitrios Soudris  Design Space Exploration 2007-IC-08
Spring, J.H.
2007
The Weight-Watcher Service and its Lightweight Implementation B. Garbinato, R. Guerraoui, J. Hulaas, A. Kounine, M. Monod, J.H. Spring   Systems and Applications 2007-IC-16
Stenstrom, Per
2007
FlexCore: Utilizing Exposed Datapath Control for Effcient Computing  M. Thuresson, M. Sjalander, M. Bjork, L. Svensson, P. Larsson-Edefors, Per Stenstrom   Processor Architectures 2007-IC-03
Svensson, L.
2007
FlexCore: Utilizing Exposed Datapath Control for Effcient Computing  M. Thuresson, M. Sjalander, M. Bjork, L. Svensson, P. Larsson-Edefors, Per Stenstrom   Processor Architectures 2007-IC-03
Taptimthong, P.
2007
Design Space Exploration of Media Processors: A Parameterized Scheduler Guillermo Payá Vayá, J. Martin-Langerwerf, P. Taptimthong, Peter Pirsch  Design Space Exploration 2007-IC-06
Teich, Jürgen
2007
Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow  J. Keinert, Christian Haubelt, Jürgen Teich Memory Architectures and Memory Optimization 2007-IC-21
Theodoridis, G.
2007
The ARISE Reconfigurable Instruction Set Extensions Framework N. Vassiliadis, G. Theodoridis, S. Nikolaidis Reconfigurable Architectures 2007-IC-20
Thuresson, M.
2007
FlexCore: Utilizing Exposed Datapath Control for Effcient Computing  M. Thuresson, M. Sjalander, M. Bjork, L. Svensson, P. Larsson-Edefors, Per Stenstrom   Processor Architectures 2007-IC-03
Toprak, Z.
2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies F. Regazzoni, S. Badel, T. Eisenbarth, Johann Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, Laura Pozzi, C. Paar, Y.  Leblebici, Paolo Ienne  Cryptography 2007-IC-27
Torres, L.
2007
Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems N. Saint-Jean, Pascal Benoit, Gilles Sassatelli, L. Torres, Michel Robert  Multiprocessor Architectures 2007-IC-12
Tumeo, Antonino
2007
An Interrupt Controller for FPGA-based Multiprocessors  Antonino Tumeo, M. Branca, L. Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto   Multiprocessor Architectures 2007-IC-11
Tumeo, Antonino
2007
An Evolutionary Approach to Area-Time Optimization of FPGA designs Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo   Reconfigurable Architectures 2007-IC-19
Valero, Mateo
2007
On the Problem of Minimizing Workload Execution Time in SMT processors F.J. Cazorla, Peter M. W. Knijnenburg, R. Sakellariou, E. Fernandez, Alex Ramirez, Mateo Valero   Multiprocessor Architectures 2007-IC-09
Valero, Mateo
2007
Online Prediction of Applications Cache Utility M. Moreto, F.J. Cazorla, Alex Ramirez, Mateo Valero  Memory Architectures and Memory Optimization 2007-IC-22
Vassiliadis, N.
2007
The ARISE Reconfigurable Instruction Set Extensions Framework N. Vassiliadis, G. Theodoridis, S. Nikolaidis Reconfigurable Architectures 2007-IC-20
Vassiliadis, Stamatis
2007
Design Space Exploration of Configuration Manager for Network Processing Applications Christoforos Kachris, Stamatis Vassiliadis Design Space Exploration 2007-IC-05
Vassiliadis, Stamatis
2007
Instruction-Level Fault Tolerance Configurability Demid Borodin, Ben Juurlink, Stamatis Vassiliadis Systems and Applications 2007-IC-15
Verbauwhede, I.
2007
A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications N. Mentens, K. Sakiyama, L. Batina, B. Preneel, I. Verbauwhede  Cryptography 2007-IC-25
Wallner, S.
2007
Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity Machines S. Muhlbach, S. Wallner Cryptography 2007-IC-26
Westermann, Peter
2007
Applying Data Mapping Techniques to Vector DSPs Peter Westermann, L. Schwoerer, A. Kaufmann Processor Architectures 2007-IC-01
Xydis, S.
2007
Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme S. Xydis, George Economakos, Kiamal Pekmestzi Reconfigurable Architectures 2007-IC-18
Yongjin, Ahn
2007
Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration Lee Ganghee, Lee Seokhyun, Ahn Yongjin, Choi Kiyoung  Design Space Exploration 2007-IC-07
Zapata, E.L.
2007
Maximum and Sorted Cache Occupation Using Array Padding  E. Herruzo, E.L. Zapata, O. Plata Memory Architectures and Memory Optimization 2007-IC-23
Zompakis, N.
2007
Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems L. Papadopoulos, C. Baloukas, N. Zompakis, Dimitrios Soudris  Design Space Exploration 2007-IC-08
Apvrille, Ludovic
2008
Evaluation of ASIPs Design with LISATek Rashid Muhammad, Ludovic Apvrille, Renaud Pacalet Special Session: System Level Design for Heterogeneous Systems 2008-WS-20
Argyrides, Costas
2008
Area Reliability Trade-Off in Improved Reed Muller Coding Costas Argyrides, Stephania Loizidou, Dhiraj K. Pradhan Application Specific 2008-WS-13
Bertels, Koen
2008
System-Level Design Space Exploration of Dynamic Reconfigurable Architectures Kamana Sigdel, Mark Thompson, Andy D. Pimentel, Todor Stefanov, Koen Bertels  System Modeling and Design 2008-WS-31
Bhattacharyya, Shuvra S.
2008
Heterogeneous Design in Functional DIF William Plishker, Nimish Sane, Mary Kiemb, Shuvra S. Bhattacharyya  Special Session: System Level Design for Heterogeneous Systems 2008-WS-18
Biest, Alexis Vander
2008
A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, Frederic Robert  SoC 2008-WS-10
Biles, Stuart
2008
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor Emre Özer, Ronald G. Dreslinski, Trevor Mudge, Stuart Biles, Krisztián Flautner  Architecture 2008-WS-03
Blake, Anthony
2008
Scalable Architecture for Prefix Preserving Anonymization of IP Addresses Anthony Blake, Richard Nelson Architecture 2008-WS-05
Blume, Holger
2008
ASIP-eFPGA Architecture for Multioperable GNSS Receivers Thorsten von Sydow, Holger Blume, Götz Kappen, Tobias G. Noll  Application Specific 2008-WS-15
Boulet, Pierre
2008
High Level Loop Transformations for Systematic Signal Processing Embedded Applications Calin Glitia, Pierre Boulet Special Session: System Level Design for Heterogeneous Systems 2008-WS-21
Bramann, Gero
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Brodman, James
2008
Design Issues in Parallel Array Languages for Shared Memory James Brodman, Basilio B. Fraguela, María J. Garzarán, David Padua  Special Session: Programming Multicores 2008-WS-24
Chen, Zhimin
2008
Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors Xu Guo, Zhimin Chen, Patrick Schaumont SoC 2008-WS-12
Clifford, John
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Dave, Nirav
2008
802.15.3 Transmitter: A Fast Design Cycle Using OFDM Framework in Bluespec Teemu Pitkänen, Vesa-Matti Hartikainen, Nirav Dave, Gopal Raghavan  New Frontiers 2008-WS-08
Degner, Martin
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Deprettere, Ed F.
2008
Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study Andy D. Pimentel, Todor Stefanov, Hristo Nikolov, Mark Thompson, Simon Polstra, Ed F. Deprettere   Special Session: System Level Design for Heterogeneous Systems 2008-WS-19
Domínguez, Miguel Ángel
2008
Climate and Biological Sensor Network Perfecto Mariño, Fernando Pérez-Fontán, Miguel Ángel Domínguez, Santiago Otero  Sensors and Sensor Networks 2008-WS-26
Dooly, Gerard
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Dreslinski, Ronald G.
2008
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor Emre Özer, Ronald G. Dreslinski, Trevor Mudge, Stuart Biles, Krisztián Flautner  Architecture 2008-WS-03
Ewald, Hartmut 
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Fettweis, Gerhard
2008
A Real-Time Programming Model for Heterogeneous MPSoCs Torsten Limberg, Bastian Ristau, Gerhard Fettweis SoC 2008-WS-09
Fischaber, Scott
2008
Memory-Centric Hardware Synthesis from Dataflow Models Scott Fischaber, John McAllister, Roger Woods Special Session: System Level Design for Heterogeneous Systems 2008-WS-22
Fitzpatrick, Colin
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Flautner, Krisztián
2008
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor Emre Özer, Ronald G. Dreslinski, Trevor Mudge, Stuart Biles, Krisztián Flautner  Architecture 2008-WS-03
Fraguela, Basilio B.
2008
Design Issues in Parallel Array Languages for Shared Memory James Brodman, Basilio B. Fraguela, María J. Garzarán, David Padua  Special Session: Programming Multicores 2008-WS-24
Garzarán, María J.
2008
Design Issues in Parallel Array Languages for Shared Memory James Brodman, Basilio B. Fraguela, María J. Garzarán, David Padua  Special Session: Programming Multicores 2008-WS-24
Gaydadjiev, Georgi N.
2008
Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications Sebastian Isaza, Friman Sánchez, Georgi N. Gaydadjiev, Alex Ramirez, Mateo Valero  New Frontiers 2008-WS-07
Gili, Flavio
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Glitia, Calin
2008
High Level Loop Transformations for Systematic Signal Processing Embedded Applications Calin Glitia, Pierre Boulet Special Session: System Level Design for Heterogeneous Systems 2008-WS-21
Glossner, John
2008
Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set Daniel Iancu, Mayan Moudgill, John Glossner, Jarmo Takala  Application Specific 2008-WS-14
Gora, Michael
2008
Intellectual Property Protection for Embedded Sensor Nodes Michael Gora, Eric Simpson, Patrick Schaumont System Modeling and Design 2008-WS-32
Grattan, Ken
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Grimm, Christian
2008
On the Benefit of Caching Traffic Flow Data in the Link Buffer Konstantin Septinus, Christian Grimm, Vladislav Rumyantsev, Peter Pirsch  Architecture 2008-WS-02
Guo, Xu
2008
Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors Xu Guo, Zhimin Chen, Patrick Schaumont SoC 2008-WS-12
Guzma, Vladimír
2008
Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic Vladimír Guzma, Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala  Architecture 2008-WS-04
Hämäläinen, Timo D.
2008
Application Server for Wireless Sensor Networks Janne Rintanen, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen  Sensors and Sensor Networks 2008-WS-28
Hämäläinen, Timo D.
2008
Embedded Software Architecture for Diagnosing Network and Node Failures in Wireless Sensor Networks Jukka Suhonen, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen  Sensors and Sensor Networks 2008-WS-29
Hännikäinen, Marko
2008
Application Server for Wireless Sensor Networks Janne Rintanen, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen  Sensors and Sensor Networks 2008-WS-28
Hännikäinen, Marko
2008
Embedded Software Architecture for Diagnosing Network and Node Failures in Wireless Sensor Networks Jukka Suhonen, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen  Sensors and Sensor Networks 2008-WS-29
Hänninen, Ismo
2008
Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology Ismo Hänninen, Jarmo Takala New Frontiers 2008-WS-06
Hartikainen, Vesa-Matti
2008
802.15.3 Transmitter: A Fast Design Cycle Using OFDM Framework in Bluespec Teemu Pitkänen, Vesa-Matti Hartikainen, Nirav Dave, Gopal Raghavan  New Frontiers 2008-WS-08
Iancu, Daniel
2008
Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set Daniel Iancu, Mayan Moudgill, John Glossner, Jarmo Takala  Application Specific 2008-WS-14
Isaza, Sebastian
2008
Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications Sebastian Isaza, Friman Sánchez, Georgi N. Gaydadjiev, Alex Ramirez, Mateo Valero  New Frontiers 2008-WS-07
Jääskeläinen, Pekka
2008
Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic Vladimír Guzma, Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala  Architecture 2008-WS-04
Jaddoe, Stanley
2008
Signature-Based Calibration of Analytical System-Level Performance Models Stanley Jaddoe, Andy D. Pimentel System Modeling and Design 2008-WS-30
Jesshope, Chris R.
2008
Introduction to Programming Multicores Chris R. Jesshope  Special Session: Programming Multicores 2008-WS-23
Jesshope, Chris R.
2008
An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency Chris R. Jesshope, Jean-Marc Philippe, Michiel van Tol Special Session: Programming Multicores 2008-WS-25
Kappen, Götz
2008
ASIP-eFPGA Architecture for Multioperable GNSS Receivers Thorsten von Sydow, Holger Blume, Götz Kappen, Tobias G. Noll  Application Specific 2008-WS-15
Kellomäki, Pertti
2008
Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic Vladimír Guzma, Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala  Architecture 2008-WS-04
Kiemb, Mary
2008
Heterogeneous Design in Functional DIF William Plishker, Nimish Sane, Mary Kiemb, Shuvra S. Bhattacharyya  Special Session: System Level Design for Heterogeneous Systems 2008-WS-18
Kohvakka, Mikko
2008
Embedded Software Architecture for Diagnosing Network and Node Failures in Wireless Sensor Networks Jukka Suhonen, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen  Sensors and Sensor Networks 2008-WS-29
Lewis, Elfed
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Limberg, Torsten
2008
A Real-Time Programming Model for Heterogeneous MPSoCs Torsten Limberg, Bastian Ristau, Gerhard Fettweis SoC 2008-WS-09
Lochmann, Steffen 
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Loizidou, Stephania
2008
Area Reliability Trade-Off in Improved Reed Muller Coding Costas Argyrides, Stephania Loizidou, Dhiraj K. Pradhan Application Specific 2008-WS-13
Lucas, James
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Mariño, Perfecto
2008
Climate and Biological Sensor Network Perfecto Mariño, Fernando Pérez-Fontán, Miguel Ángel Domínguez, Santiago Otero  Sensors and Sensor Networks 2008-WS-26
McAllister, John
2008
Introduction to System Level Design for Heterogeneous Systems John McAllister  Special Session: System Level Design for Heterogeneous Systems 2008-WS-16
McAllister, John
2008
Memory-Centric Hardware Synthesis from Dataflow Models Scott Fischaber, John McAllister, Roger Woods Special Session: System Level Design for Heterogeneous Systems 2008-WS-22
Merlone-Borla, Edoardo 
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Milojevic, Dragomir
2008
A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, Frederic Robert  SoC 2008-WS-10
Moudgill, Mayan
2008
Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set Daniel Iancu, Mayan Moudgill, John Glossner, Jarmo Takala  Application Specific 2008-WS-14
Mudge, Trevor
2008
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor Emre Özer, Ronald G. Dreslinski, Trevor Mudge, Stuart Biles, Krisztián Flautner  Architecture 2008-WS-03
Muhammad, Rashid
2008
Evaluation of ASIPs Design with LISATek Rashid Muhammad, Ludovic Apvrille, Renaud Pacalet Special Session: System Level Design for Heterogeneous Systems 2008-WS-20
Nelson, Richard
2008
Scalable Architecture for Prefix Preserving Anonymization of IP Addresses Anthony Blake, Richard Nelson Architecture 2008-WS-05
Neuendorffer, Stephen
2008
Streaming Systems in FPGAs Stephen Neuendorffer, Kees Vissers Special Session: System Level Design for Heterogeneous Systems 2008-WS-17
Nikolov, Hristo
2008
Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study Andy D. Pimentel, Todor Stefanov, Hristo Nikolov, Mark Thompson, Simon Polstra, Ed F. Deprettere   Special Session: System Level Design for Heterogeneous Systems 2008-WS-19
Noll, Tobias G.
2008
ASIP-eFPGA Architecture for Multioperable GNSS Receivers Thorsten von Sydow, Holger Blume, Götz Kappen, Tobias G. Noll  Application Specific 2008-WS-15
Otero, Santiago
2008
Climate and Biological Sensor Network Perfecto Mariño, Fernando Pérez-Fontán, Miguel Ángel Domínguez, Santiago Otero  Sensors and Sensor Networks 2008-WS-26
Özer, Emre
2008
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor Emre Özer, Ronald G. Dreslinski, Trevor Mudge, Stuart Biles, Krisztián Flautner  Architecture 2008-WS-03
Pacalet, Renaud
2008
Evaluation of ASIPs Design with LISATek Rashid Muhammad, Ludovic Apvrille, Renaud Pacalet Special Session: System Level Design for Heterogeneous Systems 2008-WS-20
Padua, David
2008
Design Issues in Parallel Array Languages for Shared Memory James Brodman, Basilio B. Fraguela, María J. Garzarán, David Padua  Special Session: Programming Multicores 2008-WS-24
Palumbo, Francesca
2008
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs Francesca Palumbo, Simone Secchi, Danilo Pani, Luigi Raffo  SoC 2008-WS-11
Pani, Danilo
2008
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs Francesca Palumbo, Simone Secchi, Danilo Pani, Luigi Raffo  SoC 2008-WS-11
Patt, Yale
2008
Can They Be Fixed: Some Thoughts After 40 Years in the Business Yale Patt  SAMOS VIII - Beachnote 2008-WS-01
Pérez-Fontán, Fernando
2008
Climate and Biological Sensor Network Perfecto Mariño, Fernando Pérez-Fontán, Miguel Ángel Domínguez, Santiago Otero  Sensors and Sensor Networks 2008-WS-26
Philippe, Jean-Marc
2008
An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency Chris R. Jesshope, Jean-Marc Philippe, Michiel van Tol Special Session: Programming Multicores 2008-WS-25
Pimentel, Andy D.
2008
Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study Andy D. Pimentel, Todor Stefanov, Hristo Nikolov, Mark Thompson, Simon Polstra, Ed F. Deprettere   Special Session: System Level Design for Heterogeneous Systems 2008-WS-19
Pimentel, Andy D.
2008
Signature-Based Calibration of Analytical System-Level Performance Models Stanley Jaddoe, Andy D. Pimentel System Modeling and Design 2008-WS-30
Pimentel, Andy D.
2008
System-Level Design Space Exploration of Dynamic Reconfigurable Architectures Kamana Sigdel, Mark Thompson, Andy D. Pimentel, Todor Stefanov, Koen Bertels  System Modeling and Design 2008-WS-31
Pirsch, Peter
2008
On the Benefit of Caching Traffic Flow Data in the Link Buffer Konstantin Septinus, Christian Grimm, Vladislav Rumyantsev, Peter Pirsch  Architecture 2008-WS-02
Pitkänen, Teemu
2008
802.15.3 Transmitter: A Fast Design Cycle Using OFDM Framework in Bluespec Teemu Pitkänen, Vesa-Matti Hartikainen, Nirav Dave, Gopal Raghavan  New Frontiers 2008-WS-08
Plishker, William
2008
Heterogeneous Design in Functional DIF William Plishker, Nimish Sane, Mary Kiemb, Shuvra S. Bhattacharyya  Special Session: System Level Design for Heterogeneous Systems 2008-WS-18
Polstra, Simon
2008
Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study Andy D. Pimentel, Todor Stefanov, Hristo Nikolov, Mark Thompson, Simon Polstra, Ed F. Deprettere   Special Session: System Level Design for Heterogeneous Systems 2008-WS-19
Pradhan, Dhiraj K.
2008
Area Reliability Trade-Off in Improved Reed Muller Coding Costas Argyrides, Stephania Loizidou, Dhiraj K. Pradhan Application Specific 2008-WS-13
Raffo, Luigi
2008
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs Francesca Palumbo, Simone Secchi, Danilo Pani, Luigi Raffo  SoC 2008-WS-11
Raghavan, Gopal
2008
802.15.3 Transmitter: A Fast Design Cycle Using OFDM Framework in Bluespec Teemu Pitkänen, Vesa-Matti Hartikainen, Nirav Dave, Gopal Raghavan  New Frontiers 2008-WS-08
Ramirez, Alex
2008
Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications Sebastian Isaza, Friman Sánchez, Georgi N. Gaydadjiev, Alex Ramirez, Mateo Valero  New Frontiers 2008-WS-07
Richard, Alienor
2008
A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, Frederic Robert  SoC 2008-WS-10
Rintanen, Janne
2008
Application Server for Wireless Sensor Networks Janne Rintanen, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen  Sensors and Sensor Networks 2008-WS-28
Ristau, Bastian
2008
A Real-Time Programming Model for Heterogeneous MPSoCs Torsten Limberg, Bastian Ristau, Gerhard Fettweis SoC 2008-WS-09
Robert, Frederic
2008
A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, Frederic Robert  SoC 2008-WS-10
Rumyantsev, Vladislav
2008
On the Benefit of Caching Traffic Flow Data in the Link Buffer Konstantin Septinus, Christian Grimm, Vladislav Rumyantsev, Peter Pirsch  Architecture 2008-WS-02
Sánchez, Friman
2008
Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications Sebastian Isaza, Friman Sánchez, Georgi N. Gaydadjiev, Alex Ramirez, Mateo Valero  New Frontiers 2008-WS-07
Sane, Nimish
2008
Heterogeneous Design in Functional DIF William Plishker, Nimish Sane, Mary Kiemb, Shuvra S. Bhattacharyya  Special Session: System Level Design for Heterogeneous Systems 2008-WS-18
Schaumont, Patrick
2008
Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors Xu Guo, Zhimin Chen, Patrick Schaumont SoC 2008-WS-12
Schaumont, Patrick
2008
Intellectual Property Protection for Embedded Sensor Nodes Michael Gora, Eric Simpson, Patrick Schaumont System Modeling and Design 2008-WS-32
Secchi, Simone
2008
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs Francesca Palumbo, Simone Secchi, Danilo Pani, Luigi Raffo  SoC 2008-WS-11
Septinus, Konstantin
2008
On the Benefit of Caching Traffic Flow Data in the Link Buffer Konstantin Septinus, Christian Grimm, Vladislav Rumyantsev, Peter Pirsch  Architecture 2008-WS-02
Sigdel, Kamana
2008
System-Level Design Space Exploration of Dynamic Reconfigurable Architectures Kamana Sigdel, Mark Thompson, Andy D. Pimentel, Todor Stefanov, Koen Bertels  System Modeling and Design 2008-WS-31
Simpson, Eric
2008
Intellectual Property Protection for Embedded Sensor Nodes Michael Gora, Eric Simpson, Patrick Schaumont System Modeling and Design 2008-WS-32
Stefanov, Todor
2008
Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study Andy D. Pimentel, Todor Stefanov, Hristo Nikolov, Mark Thompson, Simon Polstra, Ed F. Deprettere   Special Session: System Level Design for Heterogeneous Systems 2008-WS-19
Stefanov, Todor
2008
System-Level Design Space Exploration of Dynamic Reconfigurable Architectures Kamana Sigdel, Mark Thompson, Andy D. Pimentel, Todor Stefanov, Koen Bertels  System Modeling and Design 2008-WS-31
Suhonen, Jukka
2008
Application Server for Wireless Sensor Networks Janne Rintanen, Jukka Suhonen, Marko Hännikäinen, Timo D. Hämäläinen  Sensors and Sensor Networks 2008-WS-28
Suhonen, Jukka
2008
Embedded Software Architecture for Diagnosing Network and Node Failures in Wireless Sensor Networks Jukka Suhonen, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen  Sensors and Sensor Networks 2008-WS-29
Sun, Tong
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Takala, Jarmo
2008
Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set Daniel Iancu, Mayan Moudgill, John Glossner, Jarmo Takala  Application Specific 2008-WS-14
Takala, Jarmo
2008
Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic Vladimír Guzma, Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala  Architecture 2008-WS-04
Takala, Jarmo
2008
Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology Ismo Hänninen, Jarmo Takala New Frontiers 2008-WS-06
Thompson, Mark
2008
Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study Andy D. Pimentel, Todor Stefanov, Hristo Nikolov, Mark Thompson, Simon Polstra, Ed F. Deprettere   Special Session: System Level Design for Heterogeneous Systems 2008-WS-19
Thompson, Mark
2008
System-Level Design Space Exploration of Dynamic Reconfigurable Architectures Kamana Sigdel, Mark Thompson, Andy D. Pimentel, Todor Stefanov, Koen Bertels  System Modeling and Design 2008-WS-31
Valero, Mateo
2008
Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications Sebastian Isaza, Friman Sánchez, Georgi N. Gaydadjiev, Alex Ramirez, Mateo Valero  New Frontiers 2008-WS-07
van Tol, Michiel
2008
An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency Chris R. Jesshope, Jean-Marc Philippe, Michiel van Tol Special Session: Programming Multicores 2008-WS-25
Vissers, Kees
2008
Streaming Systems in FPGAs Stephen Neuendorffer, Kees Vissers Special Session: System Level Design for Heterogeneous Systems 2008-WS-17
von Sydow, Thorsten
2008
ASIP-eFPGA Architecture for Multioperable GNSS Receivers Thorsten von Sydow, Holger Blume, Götz Kappen, Tobias G. Noll  Application Specific 2008-WS-15
Woods, Roger
2008
Memory-Centric Hardware Synthesis from Dataflow Models Scott Fischaber, John McAllister, Roger Woods Special Session: System Level Design for Heterogeneous Systems 2008-WS-22
Zhao, Weizhong
2008
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors Elfed Lewis, John Clifford, Colin Fitzpatrick, Gerard Dooly, Weizhong Zhao, Tong Sun, Ken Grattan, James Lucas, Martin Degner, Hartmut Ewald, Steffen Lochmann, Gero Bramann,  Edoardo Merlone-Borla, Flavio Gili Sensors and Sensor Networks 2008-WS-27
Antikainen, Juho
2008
Fine-grained Application-speci c Instruction Set Processor Design for the K-best List Sphere Detector Algorithm Juho Antikainen, Perttu Salmela, Olli Silven, Markku Juntti, Jarmo Takala, Markus Myllylä   Processor Architecture 2008-IC-17
Ballapuram, Chinnakrishnan S.
2008
Improving TLB Energy for Java Applications on JVM Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee Memory and Caches 2008-IC-31
Banerjee, Utpal
2008
Comparative Architectural Characterization of SPEC CPU2000 and CPU2006 Benchmarks on the Intel Core 2 Duo Processor Arun Kejariwal, Alexander V. Veidenbaum, Xinmin Tian, Milind Girkar, Utpal Banerjee  Processor Architecture 2008-IC-20
Barre, Jonathan
2008
An Architecture for the Simultaneous Execution of Hard Real-Time Threads  Jonathan Barre, Christine Rochange, Pascal Sainrat Embedded Parallel Systems 2008-IC-06
Beiu, Valeriu
2008
On Brain-inspired Hybrid Topologies for Nano-architectures – A Rent’s Rule Approach – Valeriu Beiu, Basheer A. M. Madappuram, Martin McGinnity Network on a Chip 2008-IC-08
Bernard, Thomas A. M.
2008
A General Model of Concurrency and its Implementation as Many-core Dynamic RISC Processors Thomas A. M. Bernard, K. Bousias, L. Guang, Chris R. Jesshope, M. Lankamp, M. W. van Tol, L. Zhang   Embedded Parallel Systems 2008-IC-04
Bertels, Koen
2008
A Clustering Method for the Identification of Convex Disconnected Multiple Input Multiple Output Instructions Carlo Galuzzi, Dimitris Theodoropoulos, Koen Bertels Design Space Exploration 2008-IC-12
Blume, Holger
2008
Perceptual Feature based Music Classification - A DSP Perspective for a New Type of Application Holger Blume, M. Haller, Martin Botteck, W. Theimer  Applications 2008-IC-15
Botteck, Martin
2008
Perceptual Feature based Music Classification - A DSP Perspective for a New Type of Application Holger Blume, M. Haller, Martin Botteck, W. Theimer  Applications 2008-IC-15
Bousias, K.
2008
A General Model of Concurrency and its Implementation as Many-core Dynamic RISC Processors Thomas A. M. Bernard, K. Bousias, L. Guang, Chris R. Jesshope, M. Lankamp, M. W. van Tol, L. Zhang   Embedded Parallel Systems 2008-IC-04
Busonera, Giovanni
2008
Exploiting Partial Reconfiguration for Flexible Software Debugging Giovanni Busonera, Alessandro Forin, Richard Neil Pittman Reconfigurable Computing 2008-IC-25
Chakrabarti, Chaitali
2008
A Parameterized Dataflow Language Extension for Embedded Streaming Systems Yuan Lin, Yoonseo Choi, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti  Embedded Parallel Systems 2008-IC-05
Cheung, Peter Y.K.
2008
Systematic Design Space Exploration for Customisable Multi-Processor Architectures Ben Cope, Peter Y.K. Cheung, Wayne Luk Design Space Exploration 2008-IC-11
Choi, Yoonseo
2008
A Parameterized Dataflow Language Extension for Embedded Streaming Systems Yuan Lin, Yoonseo Choi, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti  Embedded Parallel Systems 2008-IC-05
Chureau, Alexandre
2008
An Intermediate Format for Automatic Generation of MPSoC Virtual Prototypes Alexandre Chureau, Frederic Petrot  Multiprocessors 2008-IC-24
Cope, Ben
2008
Systematic Design Space Exploration for Customisable Multi-Processor Architectures Ben Cope, Peter Y.K. Cheung, Wayne Luk Design Space Exploration 2008-IC-11
Corbetta, Simone
2008
A Light–Weight Network–on–Chip Architecture for Dynamically Reconfigurable Systems Simone Corbetta, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto  Network on a Chip 2008-IC-10
Coutinho, J. G. F.
2008
Reconfigurable Design with Clock Gating W.G. Osborne, Wayne Luk, J. G. F. Coutinho, O. Mencer  Reconfigurable Computing 2008-IC-27
Economakos, George
2008
An Instruction Set Extension for Java Bytecodes Translation Acceleration Isidoros Sideris, Kiamal Pekmestzi, George Economakos Processor Architecture 2008-IC-18
Eltawil, Ahmed
2008
Architectural and Algorithm level Fault Tolerant Techniques for Low Power High Yield Multimedia Devices Mohammad A. Makhzan (Avesta Sasan), Ahmed Eltawil, Fadi J. Kurdahi Processor Architecture 2008-IC-19
Ferrandi, Fabrizio
2008
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems Antonino Tumeo, Christian Pilato, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi  Multiprocessors 2008-IC-21
Forin, Alessandro
2008
Exploiting Partial Reconfiguration for Flexible Software Debugging Giovanni Busonera, Alessandro Forin, Richard Neil Pittman Reconfigurable Computing 2008-IC-25
Galuzzi, Carlo
2008
A Clustering Method for the Identification of Convex Disconnected Multiple Input Multiple Output Instructions Carlo Galuzzi, Dimitris Theodoropoulos, Koen Bertels Design Space Exploration 2008-IC-12
Garside, Jim
2008
An Adaptive Bloom Filter Cache Partitioning Scheme for Multicore Architectures Konstantinos Nikas, Matthew Horsnell, Jim Garside Embedded Parallel Systems 2008-IC-07
Gaudiot, Jean-Luc
2008
A Centralized Cache Miss Driven Technique to Improve Processor Power Dissipation Houman Homayoun, Mohammad Makhzan, Jean-Luc Gaudiot, Alexander V. Veidenbaum  Memory and Caches 2008-IC-28
Gaydadjiev, Georgi N.
2008
ImpBench: A novel benchmark suite for biomedical, microelectronic implants Christos Strydis, Christoforos Kachris, Georgi N. Gaydadjiev Applications 2008-IC-14
Giefers, Heiner
2008
Realizing Reconfigurable Mesh Algorithms on Softcore Arrays Heiner Giefers, Marco Platzner Network on a Chip 2008-IC-09
Girkar, Milind
2008
Comparative Architectural Characterization of SPEC CPU2000 and CPU2006 Benchmarks on the Intel Core 2 Duo Processor Arun Kejariwal, Alexander V. Veidenbaum, Xinmin Tian, Milind Girkar, Utpal Banerjee  Processor Architecture 2008-IC-20
Glass, Michael
2008
Multi-Objective Routing and Topology Optimization in Networked Embedded Systems Michael Glass, Martin Lukasiewycz, Rolf Wanka, Christian Haubelt, Jürgen Teich  Design Space Exploration 2008-IC-13
Guang, L.
2008
A General Model of Concurrency and its Implementation as Many-core Dynamic RISC Processors Thomas A. M. Bernard, K. Bousias, L. Guang, Chris R. Jesshope, M. Lankamp, M. W. van Tol, L. Zhang   Embedded Parallel Systems 2008-IC-04
Haller, M.
2008
Perceptual Feature based Music Classification - A DSP Perspective for a New Type of Application Holger Blume, M. Haller, Martin Botteck, W. Theimer  Applications 2008-IC-15
Haubelt, Christian
2008
Multi-Objective Routing and Topology Optimization in Networked Embedded Systems Michael Glass, Martin Lukasiewycz, Rolf Wanka, Christian Haubelt, Jürgen Teich  Design Space Exploration 2008-IC-13
Herkersdorf, Andreas
2008
Improving Memory Subsystem Performance in Network Processors with Smart Packet Segmentation Kimon Karras, Daniel Llorente, Thomas Wild, Andreas Herkersdorf  Memory and Caches 2008-IC-30
Homayoun, Houman
2008
A Centralized Cache Miss Driven Technique to Improve Processor Power Dissipation Houman Homayoun, Mohammad Makhzan, Jean-Luc Gaudiot, Alexander V. Veidenbaum  Memory and Caches 2008-IC-28
Horsnell, Matthew
2008
An Adaptive Bloom Filter Cache Partitioning Scheme for Multicore Architectures Konstantinos Nikas, Matthew Horsnell, Jim Garside Embedded Parallel Systems 2008-IC-07
Hou, Chaohuan
2008
A Priority-Expression-Based Burst Scheduling of Memory Reordering Access Jun Pang, Lei Yang, Lei Shi, Tiejun Zhang, Donghui Wang, Chaohuan Hou   Memory and Caches 2008-IC-29
Janhunen, Janne
2008
Software Defined Radio Implementation of K-best List Sphere Detector Algorithm Janne Janhunen, Olli Silven, Markku Juntti, Markus Myllylä  Applications 2008-IC-16
Jeremiassen, Tor
2008
Challenges in Embedded System Simulation Tor Jeremiassen  SAMOS VIII - Keynote 2008-IC-02
Jesshope, Chris R.
2008
A General Model of Concurrency and its Implementation as Many-core Dynamic RISC Processors Thomas A. M. Bernard, K. Bousias, L. Guang, Chris R. Jesshope, M. Lankamp, M. W. van Tol, L. Zhang   Embedded Parallel Systems 2008-IC-04
Juntti, Markku
2008
Software Defined Radio Implementation of K-best List Sphere Detector Algorithm Janne Janhunen, Olli Silven, Markku Juntti, Markus Myllylä  Applications 2008-IC-16
Juntti, Markku
2008
Fine-grained Application-speci c Instruction Set Processor Design for the K-best List Sphere Detector Algorithm Juho Antikainen, Perttu Salmela, Olli Silven, Markku Juntti, Jarmo Takala, Markus Myllylä   Processor Architecture 2008-IC-17
Kachris, Christoforos
2008
ImpBench: A novel benchmark suite for biomedical, microelectronic implants Christos Strydis, Christoforos Kachris, Georgi N. Gaydadjiev Applications 2008-IC-14
Karras, Kimon
2008
Improving Memory Subsystem Performance in Network Processors with Smart Packet Segmentation Kimon Karras, Daniel Llorente, Thomas Wild, Andreas Herkersdorf  Memory and Caches 2008-IC-30
Katevenis, Manolis G.H.
2008
Towards Unified Mechanisms for Inter-Processor Communication Manolis G.H. Katevenis  SAMOS VIII - Keynote 2008-IC-03
Kejariwal, Arun
2008
Comparative Architectural Characterization of SPEC CPU2000 and CPU2006 Benchmarks on the Intel Core 2 Duo Processor Arun Kejariwal, Alexander V. Veidenbaum, Xinmin Tian, Milind Girkar, Utpal Banerjee  Processor Architecture 2008-IC-20
Kurdahi, Fadi J.
2008
Architectural and Algorithm level Fault Tolerant Techniques for Low Power High Yield Multimedia Devices Mohammad A. Makhzan (Avesta Sasan), Ahmed Eltawil, Fadi J. Kurdahi Processor Architecture 2008-IC-19
Lankamp, M.
2008
A General Model of Concurrency and its Implementation as Many-core Dynamic RISC Processors Thomas A. M. Bernard, K. Bousias, L. Guang, Chris R. Jesshope, M. Lankamp, M. W. van Tol, L. Zhang   Embedded Parallel Systems 2008-IC-04
Lanzi, Pier Luca
2008
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems Antonino Tumeo, Christian Pilato, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi  Multiprocessors 2008-IC-21
Lee, Hsien-Hsin S.
2008
Improving TLB Energy for Java Applications on JVM Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee Memory and Caches 2008-IC-31
Lin, Yuan
2008
A Parameterized Dataflow Language Extension for Embedded Streaming Systems Yuan Lin, Yoonseo Choi, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti  Embedded Parallel Systems 2008-IC-05
Llorente, Daniel
2008
Improving Memory Subsystem Performance in Network Processors with Smart Packet Segmentation Kimon Karras, Daniel Llorente, Thomas Wild, Andreas Herkersdorf  Memory and Caches 2008-IC-30
Luk, Wayne
2008
Systematic Design Space Exploration for Customisable Multi-Processor Architectures Ben Cope, Peter Y.K. Cheung, Wayne Luk Design Space Exploration 2008-IC-11
Luk, Wayne
2008
Reconfigurable Design with Clock Gating W.G. Osborne, Wayne Luk, J. G. F. Coutinho, O. Mencer  Reconfigurable Computing 2008-IC-27
Lukasiewycz, Martin
2008
Multi-Objective Routing and Topology Optimization in Networked Embedded Systems Michael Glass, Martin Lukasiewycz, Rolf Wanka, Christian Haubelt, Jürgen Teich  Design Space Exploration 2008-IC-13
Madappuram, Basheer A. M.
2008
On Brain-inspired Hybrid Topologies for Nano-architectures – A Rent’s Rule Approach – Valeriu Beiu, Basheer A. M. Madappuram, Martin McGinnity Network on a Chip 2008-IC-08
Mahlke, Scott
2008
A Parameterized Dataflow Language Extension for Embedded Streaming Systems Yuan Lin, Yoonseo Choi, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti  Embedded Parallel Systems 2008-IC-05
Makhzan (Avesta Sasan), Mohammad A.
2008
Architectural and Algorithm level Fault Tolerant Techniques for Low Power High Yield Multimedia Devices Mohammad A. Makhzan (Avesta Sasan), Ahmed Eltawil, Fadi J. Kurdahi Processor Architecture 2008-IC-19
Makhzan, Mohammad
2008
A Centralized Cache Miss Driven Technique to Improve Processor Power Dissipation Houman Homayoun, Mohammad Makhzan, Jean-Luc Gaudiot, Alexander V. Veidenbaum  Memory and Caches 2008-IC-28
McGinnity, Martin
2008
On Brain-inspired Hybrid Topologies for Nano-architectures – A Rent’s Rule Approach – Valeriu Beiu, Basheer A. M. Madappuram, Martin McGinnity Network on a Chip 2008-IC-08
Mencer, O.
2008
Reconfigurable Design with Clock Gating W.G. Osborne, Wayne Luk, J. G. F. Coutinho, O. Mencer  Reconfigurable Computing 2008-IC-27
Merker, Renate
2008
A Cost Model for Partial Dynamic Reconfiguration  Markus Rullmann, Renate Merker Reconfigurable Computing 2008-IC-26
Mudge, Trevor
2008
PicoServer - Building a Compact Energy Efficient Multiprocessor Trevor Mudge  SAMOS VIII - Keynote 2008-IC-01
Mudge, Trevor
2008
A Parameterized Dataflow Language Extension for Embedded Streaming Systems Yuan Lin, Yoonseo Choi, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti  Embedded Parallel Systems 2008-IC-05
Myllylä, Markus
2008
Software Defined Radio Implementation of K-best List Sphere Detector Algorithm Janne Janhunen, Olli Silven, Markku Juntti, Markus Myllylä  Applications 2008-IC-16
Myllylä, Markus
2008
Fine-grained Application-speci c Instruction Set Processor Design for the K-best List Sphere Detector Algorithm Juho Antikainen, Perttu Salmela, Olli Silven, Markku Juntti, Jarmo Takala, Markus Myllylä   Processor Architecture 2008-IC-17
Nikas, Konstantinos
2008
An Adaptive Bloom Filter Cache Partitioning Scheme for Multicore Architectures Konstantinos Nikas, Matthew Horsnell, Jim Garside Embedded Parallel Systems 2008-IC-07
Osborne, W.G.
2008
Reconfigurable Design with Clock Gating W.G. Osborne, Wayne Luk, J. G. F. Coutinho, O. Mencer  Reconfigurable Computing 2008-IC-27
Palermo, Gianluca
2008
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria Multiprocessors 2008-IC-22
Pang, Jun
2008
A Priority-Expression-Based Burst Scheduling of Memory Reordering Access Jun Pang, Lei Yang, Lei Shi, Tiejun Zhang, Donghui Wang, Chaohuan Hou   Memory and Caches 2008-IC-29
Pekmestzi, Kiamal
2008
An Instruction Set Extension for Java Bytecodes Translation Acceleration Isidoros Sideris, Kiamal Pekmestzi, George Economakos Processor Architecture 2008-IC-18
Petrot, Frederic
2008
An Intermediate Format for Automatic Generation of MPSoC Virtual Prototypes Alexandre Chureau, Frederic Petrot  Multiprocessors 2008-IC-24
Pilato, Christian
2008
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems Antonino Tumeo, Christian Pilato, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi  Multiprocessors 2008-IC-21
Pittman, Richard Neil
2008
Exploiting Partial Reconfiguration for Flexible Software Debugging Giovanni Busonera, Alessandro Forin, Richard Neil Pittman Reconfigurable Computing 2008-IC-25
Platzner, Marco
2008
Realizing Reconfigurable Mesh Algorithms on Softcore Arrays Heiner Giefers, Marco Platzner Network on a Chip 2008-IC-09
Rana, Vincenzo
2008
A Light–Weight Network–on–Chip Architecture for Dynamically Reconfigurable Systems Simone Corbetta, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto  Network on a Chip 2008-IC-10
Rochange, Christine
2008
An Architecture for the Simultaneous Execution of Hard Real-Time Threads  Jonathan Barre, Christine Rochange, Pascal Sainrat Embedded Parallel Systems 2008-IC-06
Rullmann, Markus
2008
A Cost Model for Partial Dynamic Reconfiguration  Markus Rullmann, Renate Merker Reconfigurable Computing 2008-IC-26
Sainrat, Pascal
2008
An Architecture for the Simultaneous Execution of Hard Real-Time Threads  Jonathan Barre, Christine Rochange, Pascal Sainrat Embedded Parallel Systems 2008-IC-06
Salmela, Perttu
2008
Fine-grained Application-speci c Instruction Set Processor Design for the K-best List Sphere Detector Algorithm Juho Antikainen, Perttu Salmela, Olli Silven, Markku Juntti, Jarmo Takala, Markus Myllylä   Processor Architecture 2008-IC-17
Santambrogio, Marco D.
2008
A Light–Weight Network–on–Chip Architecture for Dynamically Reconfigurable Systems Simone Corbetta, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto  Network on a Chip 2008-IC-10
Sciuto, Donatella
2008
A Light–Weight Network–on–Chip Architecture for Dynamically Reconfigurable Systems Simone Corbetta, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto  Network on a Chip 2008-IC-10
Sciuto, Donatella
2008
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems Antonino Tumeo, Christian Pilato, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi  Multiprocessors 2008-IC-21
Shi, Lei
2008
A Priority-Expression-Based Burst Scheduling of Memory Reordering Access Jun Pang, Lei Yang, Lei Shi, Tiejun Zhang, Donghui Wang, Chaohuan Hou   Memory and Caches 2008-IC-29
Sideris, Isidoros
2008
An Instruction Set Extension for Java Bytecodes Translation Acceleration Isidoros Sideris, Kiamal Pekmestzi, George Economakos Processor Architecture 2008-IC-18
Silvano, Cristina
2008
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria Multiprocessors 2008-IC-22
Silven, Olli
2008
Software Defined Radio Implementation of K-best List Sphere Detector Algorithm Janne Janhunen, Olli Silven, Markku Juntti, Markus Myllylä  Applications 2008-IC-16
Silven, Olli
2008
Fine-grained Application-speci c Instruction Set Processor Design for the K-best List Sphere Detector Algorithm Juho Antikainen, Perttu Salmela, Olli Silven, Markku Juntti, Jarmo Takala, Markus Myllylä   Processor Architecture 2008-IC-17
Stenstrom, Per
2008
Efficient Management of Speculative Data in Hardware Transactional Memory Systems M. M. Waliullah, Per Stenstrom Multiprocessors 2008-IC-23
Strydis, Christos
2008
ImpBench: A novel benchmark suite for biomedical, microelectronic implants Christos Strydis, Christoforos Kachris, Georgi N. Gaydadjiev Applications 2008-IC-14
Takala, Jarmo
2008
Fine-grained Application-speci c Instruction Set Processor Design for the K-best List Sphere Detector Algorithm Juho Antikainen, Perttu Salmela, Olli Silven, Markku Juntti, Jarmo Takala, Markus Myllylä   Processor Architecture 2008-IC-17
Teich, Jürgen
2008
Multi-Objective Routing and Topology Optimization in Networked Embedded Systems Michael Glass, Martin Lukasiewycz, Rolf Wanka, Christian Haubelt, Jürgen Teich  Design Space Exploration 2008-IC-13
Theimer, W.
2008
Perceptual Feature based Music Classification - A DSP Perspective for a New Type of Application Holger Blume, M. Haller, Martin Botteck, W. Theimer  Applications 2008-IC-15
Theodoropoulos, Dimitris
2008
A Clustering Method for the Identification of Convex Disconnected Multiple Input Multiple Output Instructions Carlo Galuzzi, Dimitris Theodoropoulos, Koen Bertels Design Space Exploration 2008-IC-12
Tian, Xinmin
2008
Comparative Architectural Characterization of SPEC CPU2000 and CPU2006 Benchmarks on the Intel Core 2 Duo Processor Arun Kejariwal, Alexander V. Veidenbaum, Xinmin Tian, Milind Girkar, Utpal Banerjee  Processor Architecture 2008-IC-20
Tumeo, Antonino
2008
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems Antonino Tumeo, Christian Pilato, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi  Multiprocessors 2008-IC-21
van Tol, M. W.
2008
A General Model of Concurrency and its Implementation as Many-core Dynamic RISC Processors Thomas A. M. Bernard, K. Bousias, L. Guang, Chris R. Jesshope, M. Lankamp, M. W. van Tol, L. Zhang   Embedded Parallel Systems 2008-IC-04
Veidenbaum, Alexander V.
2008
Comparative Architectural Characterization of SPEC CPU2000 and CPU2006 Benchmarks on the Intel Core 2 Duo Processor Arun Kejariwal, Alexander V. Veidenbaum, Xinmin Tian, Milind Girkar, Utpal Banerjee  Processor Architecture 2008-IC-20
Veidenbaum, Alexander V.
2008
A Centralized Cache Miss Driven Technique to Improve Processor Power Dissipation Houman Homayoun, Mohammad Makhzan, Jean-Luc Gaudiot, Alexander V. Veidenbaum  Memory and Caches 2008-IC-28
Waliullah, M. M.
2008
Efficient Management of Speculative Data in Hardware Transactional Memory Systems M. M. Waliullah, Per Stenstrom Multiprocessors 2008-IC-23
Wang, Donghui
2008
A Priority-Expression-Based Burst Scheduling of Memory Reordering Access Jun Pang, Lei Yang, Lei Shi, Tiejun Zhang, Donghui Wang, Chaohuan Hou   Memory and Caches 2008-IC-29
Wanka, Rolf
2008
Multi-Objective Routing and Topology Optimization in Networked Embedded Systems Michael Glass, Martin Lukasiewycz, Rolf Wanka, Christian Haubelt, Jürgen Teich  Design Space Exploration 2008-IC-13
Wild, Thomas
2008
Improving Memory Subsystem Performance in Network Processors with Smart Packet Segmentation Kimon Karras, Daniel Llorente, Thomas Wild, Andreas Herkersdorf  Memory and Caches 2008-IC-30
Yang, Lei
2008
A Priority-Expression-Based Burst Scheduling of Memory Reordering Access Jun Pang, Lei Yang, Lei Shi, Tiejun Zhang, Donghui Wang, Chaohuan Hou   Memory and Caches 2008-IC-29
Zaccaria, Vittorio
2008
An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria Multiprocessors 2008-IC-22
Zhang, L.
2008
A General Model of Concurrency and its Implementation as Many-core Dynamic RISC Processors Thomas A. M. Bernard, K. Bousias, L. Guang, Chris R. Jesshope, M. Lankamp, M. W. van Tol, L. Zhang   Embedded Parallel Systems 2008-IC-04
Zhang, Tiejun
2008
A Priority-Expression-Based Burst Scheduling of Memory Reordering Access Jun Pang, Lei Yang, Lei Shi, Tiejun Zhang, Donghui Wang, Chaohuan Hou   Memory and Caches 2008-IC-29
Agarwal, Aabhas S.
2009
Prediction in Dynamic SDRAM Controller Policies Ying Xu, Aabhas S. Agarwal, Brian T. Davis VLSI Architectures Design 2009-WS-14
Agarwal, Nainesh
2009
Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing Nainesh Agarwal, Nikitas J. Dimopoulos VLSI Architectures Design 2009-WS-12
Ahonen, Tapani
2009
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi  Multi/Many Cores Architectures 2009-WS-10
Airoldi, Roberto
2009
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi  Multi/Many Cores Architectures 2009-WS-10
Ascheid, Gerd
2009
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr  Special Session 1: Instruction-Set Customization 2009-WS-22
Augonnet, Cédric
2009
Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System Cédric Augonnet, Samuel Thibault, Raymond Namyst, Maik Nijhuis  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-36
Avetisyan, Arutyun
2009
Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs Alexander Monakov, Arutyun Avetisyan Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-32
Ayguadé, Eduard
2009
The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors Paul M. Carpenter, Alex Ramirez, Eduard Ayguadé Architectures for Multimedia 2009-WS-03
Badia, Rosa M.
2009
Exploiting Locality on the Cell/B.E. through Bypassing Pieter Bellens, Josep M. Perez, Rosa M. Badia, Jesus Labarta  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-35
Batenburg, Kees Joost
2009
Experiences with Cell-BE and GPU for Tomography Sander van der Maar, Kees Joost Batenburg, Jan Sijbers Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-33
Bellens, Pieter
2009
Exploiting Locality on the Cell/B.E. through Bypassing Pieter Bellens, Josep M. Perez, Rosa M. Badia, Jesus Labarta  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-35
Blaauw, David
2009
Reconfigurable Multicore Server Processors for Low Power Operation Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor Mudge  Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-27
Boutellier, Jani
2009
Programmable Accelerators for Reconfigurable Video Decoder Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silven   Architectures for Multimedia 2009-WS-05
Buchty, Rainer
2009
An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems Rainer Buchty, Mario Kicherer, David Kramer, Wolfgang Karl  Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-25
Carpenter, Paul M.
2009
The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors Paul M. Carpenter, Alex Ramirez, Eduard Ayguadé Architectures for Multimedia 2009-WS-03
Carro, Luigi
2009
Introduction to the Future of Reconfigurable Computing and Processor Architectures Luigi Carro, Stephan Wong Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-24
Catthoor, Francky
2009
Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor   Architectures for Multimedia 2009-WS-06
Charot, François
2009
Constraint-Driven Identification of Application Specific Instructions in the DURASE System Kevin Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot  Special Session 1: Instruction-Set Customization 2009-WS-21
Choupani, Roya
2009
Multiple Description Scalable Coding for Video Transmission over Unreliable Networks Roya Choupani, Stephan Wong, Mehmet R. Tolun Architectures for Multimedia 2009-WS-07
Davis, Brian T.
2009
Prediction in Dynamic SDRAM Controller Policies Ying Xu, Aabhas S. Agarwal, Brian T. Davis VLSI Architectures Design 2009-WS-14
de la Lama, Carlos S.
2009
Programmable and Scalable Architecture for Graphics Processing Units Carlos S. de la Lama, Pekka Jääskeläinen, Jarmo Takala Architectures for Multimedia 2009-WS-02
Deprettere, Ed F.
2009
Introduction to Mastering Cell BE and GPU Execution Platforms Ed F. Deprettere, Ana L. Varbanescu Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-30
Deprettere, Ed F.
2009
Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell Dmitry Nadezhkin, Sjoerd Meijer, Todor Stefanov, Ed F. Deprettere  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-34
Dimopoulos, Nikitas J.
2009
Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing Nainesh Agarwal, Nikitas J. Dimopoulos VLSI Architectures Design 2009-WS-12
Dreslinski, Ronald G.
2009
Reconfigurable Multicore Server Processors for Low Power Operation Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor Mudge  Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-27
Dutta, Hritam
2009
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-31
Fick, David
2009
Reconfigurable Multicore Server Processors for Low Power Operation Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor Mudge  Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-27
Floch, Antoine
2009
Constraint-Driven Identification of Application Specific Instructions in the DURASE System Kevin Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot  Special Session 1: Instruction-Set Customization 2009-WS-21
Galuzzi, Carlo
2009
Introduction to Instruction-Set Customization Carlo Galuzzi  Special Session 1: Instruction-Set Customization 2009-WS-20
Garzia, Fabio
2009
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi  Multi/Many Cores Architectures 2009-WS-10
Gaydadjiev, Georgi N.
2009
Reconfigurable Multithreading Architectures: A Survey Pavel G. Zaykov, Georgi Kuzmanov, Georgi N. Gaydadjiev Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-29
Giorgi, Roberto
2009
Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture Roberto Giorgi, Zdravko Popovic, Nikola Puzovic Multi/Many Cores Architectures 2009-WS-09
Hammari, Elena
2009
Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor   Architectures for Multimedia 2009-WS-06
Hannig, Frank
2009
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-31
Hänninen, Ismo
2009
Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata Ismo Hänninen, Jarmo Takala VLSI Architectures Design 2009-WS-13
Heenes, Wolfgang
2009
A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA Christian Schäck, Wolfgang Heenes, Rolf Hoffmann Multi/Many Cores Architectures 2009-WS-11
Hoffmann, Rolf
2009
A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA Christian Schäck, Wolfgang Heenes, Rolf Hoffmann Multi/Many Cores Architectures 2009-WS-11
Huber, Bernhard
2009
A Comparison of NoTA and GENESYS Bernhard Huber, Roman Obermaisser Architecture Modeling and Exploration Tools 2009-WS-19
Huynh, Huynh Phung
2009
Runtime Adaptive Extensible Embedded Processors — A Survey Huynh Phung Huynh, Tulika Mitra Special Session 1: Instruction-Set Customization 2009-WS-23
Jääskeläinen, Pekka
2009
Programmable and Scalable Architecture for Graphics Processing Units Carlos S. de la Lama, Pekka Jääskeläinen, Jarmo Takala Architectures for Multimedia 2009-WS-02
Jääskeläinen, Pekka
2009
Programmable Accelerators for Reconfigurable Video Decoder Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silven   Architectures for Multimedia 2009-WS-05
Jan, Yahya
2009
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey Yahya Jan, Lech Jozwiak Architectures for Multimedia 2009-WS-04
Jozwiak, Lech
2009
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey Yahya Jan, Lech Jozwiak Architectures for Multimedia 2009-WS-04
Karl, Wolfgang
2009
An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems Rainer Buchty, Mario Kicherer, David Kramer, Wolfgang Karl  Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-25
Karlström, Per
2009
NoGAP: A Micro Architecture Construction Framework Per Karlström, Dake Liu Architecture Modeling and Exploration Tools 2009-WS-18
Karuri, Kingshuk
2009
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr  Special Session 1: Instruction-Set Customization 2009-WS-22
Kato, Shinichi
2009
Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI Shinichi Kato, Minoru Watanabe VLSI Architectures Design 2009-WS-15
Kicherer, Mario
2009
An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems Rainer Buchty, Mario Kicherer, David Kramer, Wolfgang Karl  Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-25
Kjeldsberg, Per Gunnar
2009
Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor   Architectures for Multimedia 2009-WS-06
Kramer, David
2009
An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems Rainer Buchty, Mario Kicherer, David Kramer, Wolfgang Karl  Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-25
Kuchcinski, Krzysztof
2009
Constraint-Driven Identification of Application Specific Instructions in the DURASE System Kevin Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot  Special Session 1: Instruction-Set Customization 2009-WS-21
Kuzmanov, Georgi
2009
Reconfigurable Multithreading Architectures: A Survey Pavel G. Zaykov, Georgi Kuzmanov, Georgi N. Gaydadjiev Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-29
Labarta, Jesus
2009
Exploiting Locality on the Cell/B.E. through Bypassing Pieter Bellens, Josep M. Perez, Rosa M. Badia, Jesus Labarta  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-35
Leupers, Rainer
2009
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr  Special Session 1: Instruction-Set Customization 2009-WS-22
Liu, Dake
2009
NoGAP: A Micro Architecture Construction Framework Per Karlström, Dake Liu Architecture Modeling and Exploration Tools 2009-WS-18
Mamagkakis, Stylianos
2009
Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor   Architectures for Multimedia 2009-WS-06
Martin, Kevin
2009
Constraint-Driven Identification of Application Specific Instructions in the DURASE System Kevin Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot  Special Session 1: Instruction-Set Customization 2009-WS-21
Meijer, Sjoerd
2009
Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell Dmitry Nadezhkin, Sjoerd Meijer, Todor Stefanov, Ed F. Deprettere  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-34
Membarth, Richard
2009
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-31
Meyr, Heinrich
2009
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr  Special Session 1: Instruction-Set Customization 2009-WS-22
Milojevic, Dragomir
2009
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi  Multi/Many Cores Architectures 2009-WS-10
Miniskar, Narasinga Rao
2009
Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor   Architectures for Multimedia 2009-WS-06
Mitra, Tulika
2009
Runtime Adaptive Extensible Embedded Processors — A Survey Huynh Phung Huynh, Tulika Mitra Special Session 1: Instruction-Set Customization 2009-WS-23
Monakov, Alexander
2009
Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs Alexander Monakov, Arutyun Avetisyan Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-32
Mudge, Trevor
2009
Reconfigurable Multicore Server Processors for Low Power Operation Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor Mudge  Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-27
Munaga, Satyakiran
2009
Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor   Architectures for Multimedia 2009-WS-06
Nadezhkin, Dmitry
2009
Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell Dmitry Nadezhkin, Sjoerd Meijer, Todor Stefanov, Ed F. Deprettere  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-34
Najjar, Walid A.
2009
Reconfigurable Computing in the New Age of Parallelism Walid A. Najjar, Jason Villarreal Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-28
Namyst, Raymond
2009
Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System Cédric Augonnet, Samuel Thibault, Raymond Namyst, Maik Nijhuis  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-36
Nijhuis, Maik
2009
Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System Cédric Augonnet, Samuel Thibault, Raymond Namyst, Maik Nijhuis  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-36
Nurmi, Jari
2009
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi  Multi/Many Cores Architectures 2009-WS-10
Obermaisser, Roman
2009
A Comparison of NoTA and GENESYS Bernhard Huber, Roman Obermaisser Architecture Modeling and Exploration Tools 2009-WS-19
Patt, Yale
2009
What Else Is Broken? Can We Fix It? Yale Patt  SAMOS IX - Beachnote 2009-WS-01
Perez, Josep M.
2009
Exploiting Locality on the Cell/B.E. through Bypassing Pieter Bellens, Josep M. Perez, Rosa M. Badia, Jesus Labarta  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-35
Pimentel, Andy D.
2009
Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration Toktam Taghavi, Mark Thompson, Andy D. Pimentel Architecture Modeling and Exploration Tools 2009-WS-16
Popovic, Zdravko
2009
Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture Roberto Giorgi, Zdravko Popovic, Nikola Puzovic Multi/Many Cores Architectures 2009-WS-09
Pratas, Frederico
2009
Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study Frederico Pratas, Leonel Sousa Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-26
Puzovic, Nikola
2009
Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture Roberto Giorgi, Zdravko Popovic, Nikola Puzovic Multi/Many Cores Architectures 2009-WS-09
Ramirez, Alex
2009
The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors Paul M. Carpenter, Alex Ramirez, Eduard Ayguadé Architectures for Multimedia 2009-WS-03
Reinikka, Timo
2009
Programmable Accelerators for Reconfigurable Video Decoder Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silven   Architectures for Multimedia 2009-WS-05
Rintaluoma, Tero
2009
Programmable Accelerators for Reconfigurable Video Decoder Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silven   Architectures for Multimedia 2009-WS-05
Rouvinen, Joona
2009
Programmable Accelerators for Reconfigurable Video Decoder Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silven   Architectures for Multimedia 2009-WS-05
Schäck, Christian
2009
A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA Christian Schäck, Wolfgang Heenes, Rolf Hoffmann Multi/Many Cores Architectures 2009-WS-11
Schröder, Hartmut
2009
Modeling Scalable SIMD DSPs in LISA Peter Westermann, Hartmut Schröder Architecture Modeling and Exploration Tools 2009-WS-17
Sijbers, Jan
2009
Experiences with Cell-BE and GPU for Tomography Sander van der Maar, Kees Joost Batenburg, Jan Sijbers Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-33
Silven, Olli
2009
Programmable Accelerators for Reconfigurable Video Decoder Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silven   Architectures for Multimedia 2009-WS-05
Sousa, Leonel
2009
Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study Frederico Pratas, Leonel Sousa Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-26
Stefanov, Todor
2009
Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell Dmitry Nadezhkin, Sjoerd Meijer, Todor Stefanov, Ed F. Deprettere  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-34
Sylvester, Dennis
2009
Reconfigurable Multicore Server Processors for Low Power Operation Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor Mudge  Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-27
Taghavi, Toktam
2009
Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration Toktam Taghavi, Mark Thompson, Andy D. Pimentel Architecture Modeling and Exploration Tools 2009-WS-16
Takala, Jarmo
2009
Programmable and Scalable Architecture for Graphics Processing Units Carlos S. de la Lama, Pekka Jääskeläinen, Jarmo Takala Architectures for Multimedia 2009-WS-02
Takala, Jarmo
2009
Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata Ismo Hänninen, Jarmo Takala VLSI Architectures Design 2009-WS-13
Teich, Jürgen
2009
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-31
Thibault, Samuel
2009
Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System Cédric Augonnet, Samuel Thibault, Raymond Namyst, Maik Nijhuis  Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-36
Thompson, Mark
2009
Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration Toktam Taghavi, Mark Thompson, Andy D. Pimentel Architecture Modeling and Exploration Tools 2009-WS-16
Tolun, Mehmet R.
2009
Multiple Description Scalable Coding for Video Transmission over Unreliable Networks Roya Choupani, Stephan Wong, Mehmet R. Tolun Architectures for Multimedia 2009-WS-07
Uhrig, Sascha
2009
Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC Sascha Uhrig  Multi/Many Cores Architectures 2009-WS-08
van der Maar, Sander
2009
Experiences with Cell-BE and GPU for Tomography Sander van der Maar, Kees Joost Batenburg, Jan Sijbers Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-33
Varbanescu, Ana L.
2009
Introduction to Mastering Cell BE and GPU Execution Platforms Ed F. Deprettere, Ana L. Varbanescu Special Session 3: Mastering Cell BE and GPU
Execution Platforms
2009-WS-30
Villarreal, Jason
2009
Reconfigurable Computing in the New Age of Parallelism Walid A. Najjar, Jason Villarreal Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-28
Watanabe, Minoru
2009
Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI Shinichi Kato, Minoru Watanabe VLSI Architectures Design 2009-WS-15
Westermann, Peter
2009
Modeling Scalable SIMD DSPs in LISA Peter Westermann, Hartmut Schröder Architecture Modeling and Exploration Tools 2009-WS-17
Wolinski, Christophe
2009
Constraint-Driven Identification of Application Specific Instructions in the DURASE System Kevin Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot  Special Session 1: Instruction-Set Customization 2009-WS-21
Wong, Stephan
2009
Multiple Description Scalable Coding for Video Transmission over Unreliable Networks Roya Choupani, Stephan Wong, Mehmet R. Tolun Architectures for Multimedia 2009-WS-07
Wong, Stephan
2009
Introduction to the Future of Reconfigurable Computing and Processor Architectures Luigi Carro, Stephan Wong Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-24
Xu, Ying
2009
Prediction in Dynamic SDRAM Controller Policies Ying Xu, Aabhas S. Agarwal, Brian T. Davis VLSI Architectures Design 2009-WS-14
Zaykov, Pavel G.
2009
Reconfigurable Multithreading Architectures: A Survey Pavel G. Zaykov, Georgi Kuzmanov, Georgi N. Gaydadjiev Special Session 2: The Future of Reconfigurable
Computing and Processor Architectures
2009-WS-29
Aliaga, R.J.
2009
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA R.J. Aliaga, R. Gadea, R.J. Colom, J. Cerda, N. Ferrando, V. Herrero   RECONFIGURABLE SYSTEMS 2009-IC-03
Ayguadé, Eduard
2009
OpenMP extensions for FPGA accelerators D. Cabrera, Xavier Martorell, Georgi N. Gaydadjiev, Eduard Ayguadé, D. Jimenez-Gonzalez  RECONFIGURABLE SYSTEMS 2009-IC-05
Bachmann, C.
2009
An emulation-based real-time power profiling unit for embedded software A. Genser, C. Bachmann, J. Haid, C. Steger, R. Weiss  Simulation and Emulation Techniques 2009-IC-11
Bacivarov, I.
2009
Generation and calibration of compositional performance analysis models for multi-processor systems W. Haid, M. Keller, Huang Kai, I. Bacivarov, L. Thiele  Multiprocessor Modeling and Evaluation 2009-IC-14
Balzola, P.
2009
Synchronization on heterogeneous multiprocessor systems Mayan Moudgill, V. Kalashnikov, Murugappan Senthilvelan, U. Srikantiah, Li Tak-po, P. Balzola, John Glossner   Multiprocessor Communication and Synchronization 2009-IC-19
Bekooij, Marco J.G.
2009
Inter-task communication via overlapping read and write windows for deadlock-free execution of cyclic task graphs T. Bijlsma, Marco J.G. Bekooij, Gerard J. M. Smit Multiprocessor Communication and Synchronization 2009-IC-20
Bengtsson, J.
2009
Manycore performance analysis using timed configuration graphs J. Bengtsson, B. Svensson Multiprocessor Modeling and Evaluation 2009-IC-16
Bijlsma, T.
2009
Inter-task communication via overlapping read and write windows for deadlock-free execution of cyclic task graphs T. Bijlsma, Marco J.G. Bekooij, Gerard J. M. Smit Multiprocessor Communication and Synchronization 2009-IC-20
Blume, Holger
2009
Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures Holger Flatt, I. Schmadecke, M. Kargel, Holger Blume, Peter Pirsch  Multiprocessor Communication and Synchronization 2009-IC-18
Cabrera, D.
2009
OpenMP extensions for FPGA accelerators D. Cabrera, Xavier Martorell, Georgi N. Gaydadjiev, Eduard Ayguadé, D. Jimenez-Gonzalez  RECONFIGURABLE SYSTEMS 2009-IC-05
Casseau, E.
2009
High-level synthesis for the design of FPGA-based signal processing systems E. Casseau, B. Le Gal RECONFIGURABLE SYSTEMS 2009-IC-06
Catthoor, Francky
2009
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures R. Fasthuber, Li Min, David Novo, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor   Architectures and Implementations 2009-IC-23
Cerda, J.
2009
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA R.J. Aliaga, R. Gadea, R.J. Colom, J. Cerda, N. Ferrando, V. Herrero   RECONFIGURABLE SYSTEMS 2009-IC-03
Chakrabarti, Chaitali 
2009
Customizing wide-SIMD architectures for H.264 S. Seo, Mark Woh, Scott Mahlke, Trevor Mudge, S. Vijay, Chaitali Chakrabarti   Architectures and Implementations 2009-IC-24
Chen, Sao-Jie
2009
Parallel implementation of convolution encoder for software defined radio on DSP architecture Jui-Chieh Lin, Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen, Yu-Hen Hu   Architectures and Implementations 2009-IC-25
Colom, R.J.
2009
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA R.J. Aliaga, R. Gadea, R.J. Colom, J. Cerda, N. Ferrando, V. Herrero   RECONFIGURABLE SYSTEMS 2009-IC-03
Corporaal, Henk
2009
Performance evaluation of concurrently executing parallel applications on multi-processor systems Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal  Multiprocessor Modeling and Evaluation 2009-IC-15
Daruwalla, S.
2009
Adaptive simulation sampling using an Autoregressive framework S. Daruwalla, R. Sendag, J. Yi Simulation and Emulation Techniques 2009-IC-10
Fasthuber, R.
2009
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures R. Fasthuber, Li Min, David Novo, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor   Architectures and Implementations 2009-IC-23
Ferrando, N.
2009
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA R.J. Aliaga, R. Gadea, R.J. Colom, J. Cerda, N. Ferrando, V. Herrero   RECONFIGURABLE SYSTEMS 2009-IC-03
Flatt, Holger
2009
Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures Holger Flatt, I. Schmadecke, M. Kargel, Holger Blume, Peter Pirsch  Multiprocessor Communication and Synchronization 2009-IC-18
Gadea, R.
2009
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA R.J. Aliaga, R. Gadea, R.J. Colom, J. Cerda, N. Ferrando, V. Herrero   RECONFIGURABLE SYSTEMS 2009-IC-03
Garga, G.
2009
High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures G. Garga, David Guevorkian, S.K. Nandy, H.S. Jamadagni  Architectures and Implementations 2009-IC-22
Gaydadjiev, Georgi N.
2009
OpenMP extensions for FPGA accelerators D. Cabrera, Xavier Martorell, Georgi N. Gaydadjiev, Eduard Ayguadé, D. Jimenez-Gonzalez  RECONFIGURABLE SYSTEMS 2009-IC-05
Genser, A.
2009
An emulation-based real-time power profiling unit for embedded software A. Genser, C. Bachmann, J. Haid, C. Steger, R. Weiss  Simulation and Emulation Techniques 2009-IC-11
Glossner, John
2009
Synchronization on heterogeneous multiprocessor systems Mayan Moudgill, V. Kalashnikov, Murugappan Senthilvelan, U. Srikantiah, Li Tak-po, P. Balzola, John Glossner   Multiprocessor Communication and Synchronization 2009-IC-19
Guevorkian, David
2009
High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures G. Garga, David Guevorkian, S.K. Nandy, H.S. Jamadagni  Architectures and Implementations 2009-IC-22
Ha, Soonhoi
2009
A timed HW/SW coemulation technique for fast yet accurate system verification Hoeseok Yang, Youngmin Yi, Soonhoi Ha Simulation and Emulation Techniques 2009-IC-12
Haid, J.
2009
An emulation-based real-time power profiling unit for embedded software A. Genser, C. Bachmann, J. Haid, C. Steger, R. Weiss  Simulation and Emulation Techniques 2009-IC-11
Haid, W.
2009
Generation and calibration of compositional performance analysis models for multi-processor systems W. Haid, M. Keller, Huang Kai, I. Bacivarov, L. Thiele  Multiprocessor Modeling and Evaluation 2009-IC-14
Herrero, V.
2009
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA R.J. Aliaga, R. Gadea, R.J. Colom, J. Cerda, N. Ferrando, V. Herrero   RECONFIGURABLE SYSTEMS 2009-IC-03
Hsiung, Pao-Ann
2009
Parallel implementation of convolution encoder for software defined radio on DSP architecture Jui-Chieh Lin, Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen, Yu-Hen Hu   Architectures and Implementations 2009-IC-25
Hu, Yu-Hen
2009
Parallel implementation of convolution encoder for software defined radio on DSP architecture Jui-Chieh Lin, Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen, Yu-Hen Hu   Architectures and Implementations 2009-IC-25
Jamadagni, H.S.
2009
High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures G. Garga, David Guevorkian, S.K. Nandy, H.S. Jamadagni  Architectures and Implementations 2009-IC-22
Jimenez-Gonzalez, D.
2009
OpenMP extensions for FPGA accelerators D. Cabrera, Xavier Martorell, Georgi N. Gaydadjiev, Eduard Ayguadé, D. Jimenez-Gonzalez  RECONFIGURABLE SYSTEMS 2009-IC-05
Kai, Huang
2009
Generation and calibration of compositional performance analysis models for multi-processor systems W. Haid, M. Keller, Huang Kai, I. Bacivarov, L. Thiele  Multiprocessor Modeling and Evaluation 2009-IC-14
Kalashnikov, V.
2009
Synchronization on heterogeneous multiprocessor systems Mayan Moudgill, V. Kalashnikov, Murugappan Senthilvelan, U. Srikantiah, Li Tak-po, P. Balzola, John Glossner   Multiprocessor Communication and Synchronization 2009-IC-19
Kalokerinos, G.
2009
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability G. Kalokerinos, V. Papaefstathiou, G. Nikiforos, S. Kavadias, Manolis G.H. Katevenis, D. Pnevmatikatos, Yang Xiaojun   Multiprocessor Communication and Synchronization 2009-IC-21
Kargel, M.
2009
Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures Holger Flatt, I. Schmadecke, M. Kargel, Holger Blume, Peter Pirsch  Multiprocessor Communication and Synchronization 2009-IC-18
Katevenis, Manolis G.H.
2009
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability G. Kalokerinos, V. Papaefstathiou, G. Nikiforos, S. Kavadias, Manolis G.H. Katevenis, D. Pnevmatikatos, Yang Xiaojun   Multiprocessor Communication and Synchronization 2009-IC-21
Kavadias, S.
2009
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability G. Kalokerinos, V. Papaefstathiou, G. Nikiforos, S. Kavadias, Manolis G.H. Katevenis, D. Pnevmatikatos, Yang Xiaojun   Multiprocessor Communication and Synchronization 2009-IC-21
Kaxiras, Stefanos
2009
Instruction-based reuse-distance prediction for effective cache management Pavlos Petoumenos, Georgios Keramidas, Stefanos Kaxiras Instruction Scheduling and Microarchitecture Optimizations 2009-IC-09
Keller, M.
2009
Generation and calibration of compositional performance analysis models for multi-processor systems W. Haid, M. Keller, Huang Kai, I. Bacivarov, L. Thiele  Multiprocessor Modeling and Evaluation 2009-IC-14
Keramidas, Georgios
2009
Instruction-based reuse-distance prediction for effective cache management Pavlos Petoumenos, Georgios Keramidas, Stefanos Kaxiras Instruction Scheduling and Microarchitecture Optimizations 2009-IC-09
Kumar, Akash
2009
Performance evaluation of concurrently executing parallel applications on multi-processor systems Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal  Multiprocessor Modeling and Evaluation 2009-IC-15
Le Gal, B.
2009
High-level synthesis for the design of FPGA-based signal processing systems E. Casseau, B. Le Gal RECONFIGURABLE SYSTEMS 2009-IC-06
Lin, Jui-Chieh
2009
Parallel implementation of convolution encoder for software defined radio on DSP architecture Jui-Chieh Lin, Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen, Yu-Hen Hu   Architectures and Implementations 2009-IC-25
Mahlke, Scott
2009
Customizing wide-SIMD architectures for H.264 S. Seo, Mark Woh, Scott Mahlke, Trevor Mudge, S. Vijay, Chaitali Chakrabarti   Architectures and Implementations 2009-IC-24
Mariani, G.
2009
Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques G. Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria  Multiprocessor Modeling and Evaluation 2009-IC-17
Martin, G.
2009
“Slower than you think” — The evolution of processor and SoC architectures G. Martin  SAMOS IX - Keynote 2009-IC-02
Martorell, Xavier
2009
OpenMP extensions for FPGA accelerators D. Cabrera, Xavier Martorell, Georgi N. Gaydadjiev, Eduard Ayguadé, D. Jimenez-Gonzalez  RECONFIGURABLE SYSTEMS 2009-IC-05
Mesman, Bart
2009
Performance evaluation of concurrently executing parallel applications on multi-processor systems Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal  Multiprocessor Modeling and Evaluation 2009-IC-15
Min, Li
2009
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures R. Fasthuber, Li Min, David Novo, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor   Architectures and Implementations 2009-IC-23
Moshovos, A.
2009
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors E. Safi, A. Moshovos, A. Veneris Instruction Scheduling and Microarchitecture Optimizations 2009-IC-08
Moudgill, Mayan
2009
Synchronization on heterogeneous multiprocessor systems Mayan Moudgill, V. Kalashnikov, Murugappan Senthilvelan, U. Srikantiah, Li Tak-po, P. Balzola, John Glossner   Multiprocessor Communication and Synchronization 2009-IC-19
Mudge, Trevor
2009
Customizing wide-SIMD architectures for H.264 S. Seo, Mark Woh, Scott Mahlke, Trevor Mudge, S. Vijay, Chaitali Chakrabarti   Architectures and Implementations 2009-IC-24
Mujadiya, N.V.
2009
Instruction scheduling for VLIW processors under variation scenario N.V. Mujadiya  Instruction Scheduling and Microarchitecture Optimizations 2009-IC-07
Nandy, S.K.
2009
RETHROTTLE: Execution throttling in the REDEFINE SoC architecture A.N. Satrawala, S.K. Nandy Simulation and Emulation Techniques 2009-IC-13
Nandy, S.K.
2009
High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures G. Garga, David Guevorkian, S.K. Nandy, H.S. Jamadagni  Architectures and Implementations 2009-IC-22
Nikiforos, G.
2009
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability G. Kalokerinos, V. Papaefstathiou, G. Nikiforos, S. Kavadias, Manolis G.H. Katevenis, D. Pnevmatikatos, Yang Xiaojun   Multiprocessor Communication and Synchronization 2009-IC-21
Novo, David
2009
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures R. Fasthuber, Li Min, David Novo, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor   Architectures and Implementations 2009-IC-23
Palermo, Gianluca
2009
Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques G. Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria  Multiprocessor Modeling and Evaluation 2009-IC-17
Papadimitriou, K.
2009
High-speed FPGA-based implementations of a Genetic Algorithm M. Vavouras, K. Papadimitriou, I. Papaefstathiou RECONFIGURABLE SYSTEMS 2009-IC-04
Papaefstathiou, I.
2009
High-speed FPGA-based implementations of a Genetic Algorithm M. Vavouras, K. Papadimitriou, I. Papaefstathiou RECONFIGURABLE SYSTEMS 2009-IC-04
Papaefstathiou, V.
2009
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability G. Kalokerinos, V. Papaefstathiou, G. Nikiforos, S. Kavadias, Manolis G.H. Katevenis, D. Pnevmatikatos, Yang Xiaojun   Multiprocessor Communication and Synchronization 2009-IC-21
Petoumenos, Pavlos
2009
Instruction-based reuse-distance prediction for effective cache management Pavlos Petoumenos, Georgios Keramidas, Stefanos Kaxiras Instruction Scheduling and Microarchitecture Optimizations 2009-IC-09
Pirsch, Peter
2009
Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures Holger Flatt, I. Schmadecke, M. Kargel, Holger Blume, Peter Pirsch  Multiprocessor Communication and Synchronization 2009-IC-18
Pnevmatikatos, D.
2009
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability G. Kalokerinos, V. Papaefstathiou, G. Nikiforos, S. Kavadias, Manolis G.H. Katevenis, D. Pnevmatikatos, Yang Xiaojun   Multiprocessor Communication and Synchronization 2009-IC-21
Pulli, K.
2009
Mobile visual computing K. Pulli  SAMOS IX - Keynote 2009-IC-01
Raghavan, Praveen
2009
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures R. Fasthuber, Li Min, David Novo, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor   Architectures and Implementations 2009-IC-23
Safi, E.
2009
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors E. Safi, A. Moshovos, A. Veneris Instruction Scheduling and Microarchitecture Optimizations 2009-IC-08
Satrawala, A.N.
2009
RETHROTTLE: Execution throttling in the REDEFINE SoC architecture A.N. Satrawala, S.K. Nandy Simulation and Emulation Techniques 2009-IC-13
Schmadecke, I.
2009
Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures Holger Flatt, I. Schmadecke, M. Kargel, Holger Blume, Peter Pirsch  Multiprocessor Communication and Synchronization 2009-IC-18
Sendag, R.
2009
Adaptive simulation sampling using an Autoregressive framework S. Daruwalla, R. Sendag, J. Yi Simulation and Emulation Techniques 2009-IC-10
Senthilvelan, Murugappan
2009
Synchronization on heterogeneous multiprocessor systems Mayan Moudgill, V. Kalashnikov, Murugappan Senthilvelan, U. Srikantiah, Li Tak-po, P. Balzola, John Glossner   Multiprocessor Communication and Synchronization 2009-IC-19
Seo, S.
2009
Customizing wide-SIMD architectures for H.264 S. Seo, Mark Woh, Scott Mahlke, Trevor Mudge, S. Vijay, Chaitali Chakrabarti   Architectures and Implementations 2009-IC-24
Shabbir, Ahsan
2009
Performance evaluation of concurrently executing parallel applications on multi-processor systems Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal  Multiprocessor Modeling and Evaluation 2009-IC-15
Silvano, Cristina
2009
Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques G. Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria  Multiprocessor Modeling and Evaluation 2009-IC-17
Smit, Gerard J. M.
2009
Inter-task communication via overlapping read and write windows for deadlock-free execution of cyclic task graphs T. Bijlsma, Marco J.G. Bekooij, Gerard J. M. Smit Multiprocessor Communication and Synchronization 2009-IC-20
Srikantiah, U.
2009
Synchronization on heterogeneous multiprocessor systems Mayan Moudgill, V. Kalashnikov, Murugappan Senthilvelan, U. Srikantiah, Li Tak-po, P. Balzola, John Glossner   Multiprocessor Communication and Synchronization 2009-IC-19
Steger, C.
2009
An emulation-based real-time power profiling unit for embedded software A. Genser, C. Bachmann, J. Haid, C. Steger, R. Weiss  Simulation and Emulation Techniques 2009-IC-11
Svensson, B.
2009
Manycore performance analysis using timed configuration graphs J. Bengtsson, B. Svensson Multiprocessor Modeling and Evaluation 2009-IC-16
Tak-po, Li
2009
Synchronization on heterogeneous multiprocessor systems Mayan Moudgill, V. Kalashnikov, Murugappan Senthilvelan, U. Srikantiah, Li Tak-po, P. Balzola, John Glossner   Multiprocessor Communication and Synchronization 2009-IC-19
Thiele, L.
2009
Generation and calibration of compositional performance analysis models for multi-processor systems W. Haid, M. Keller, Huang Kai, I. Bacivarov, L. Thiele  Multiprocessor Modeling and Evaluation 2009-IC-14
Van der Perre, Liesbet
2009
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures R. Fasthuber, Li Min, David Novo, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor   Architectures and Implementations 2009-IC-23
Vavouras, M.
2009
High-speed FPGA-based implementations of a Genetic Algorithm M. Vavouras, K. Papadimitriou, I. Papaefstathiou RECONFIGURABLE SYSTEMS 2009-IC-04
Veneris, A.
2009
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors E. Safi, A. Moshovos, A. Veneris Instruction Scheduling and Microarchitecture Optimizations 2009-IC-08
Vijay, S.
2009
Customizing wide-SIMD architectures for H.264 S. Seo, Mark Woh, Scott Mahlke, Trevor Mudge, S. Vijay, Chaitali Chakrabarti   Architectures and Implementations 2009-IC-24
Weiss, R.
2009
An emulation-based real-time power profiling unit for embedded software A. Genser, C. Bachmann, J. Haid, C. Steger, R. Weiss  Simulation and Emulation Techniques 2009-IC-11
Woh, Mark
2009
Customizing wide-SIMD architectures for H.264 S. Seo, Mark Woh, Scott Mahlke, Trevor Mudge, S. Vijay, Chaitali Chakrabarti   Architectures and Implementations 2009-IC-24
Xiaojun, Yang
2009
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability G. Kalokerinos, V. Papaefstathiou, G. Nikiforos, S. Kavadias, Manolis G.H. Katevenis, D. Pnevmatikatos, Yang Xiaojun   Multiprocessor Communication and Synchronization 2009-IC-21
Yang, Hoeseok
2009
A timed HW/SW coemulation technique for fast yet accurate system verification Hoeseok Yang, Youngmin Yi, Soonhoi Ha Simulation and Emulation Techniques 2009-IC-12
Yen, Mao-Hsu
2009
Parallel implementation of convolution encoder for software defined radio on DSP architecture Jui-Chieh Lin, Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen, Yu-Hen Hu   Architectures and Implementations 2009-IC-25
Yi, J.
2009
Adaptive simulation sampling using an Autoregressive framework S. Daruwalla, R. Sendag, J. Yi Simulation and Emulation Techniques 2009-IC-10
Yi, Youngmin
2009
A timed HW/SW coemulation technique for fast yet accurate system verification Hoeseok Yang, Youngmin Yi, Soonhoi Ha Simulation and Emulation Techniques 2009-IC-12
Yu, Chu
2009
Parallel implementation of convolution encoder for software defined radio on DSP architecture Jui-Chieh Lin, Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen, Yu-Hen Hu   Architectures and Implementations 2009-IC-25
Zaccaria, Vittorio
2009
Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques G. Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria  Multiprocessor Modeling and Evaluation 2009-IC-17
Alle, Mythri
2010
Enhancements for Variable N-point Streaming FFT/IFFT on REDEFINE, a Runtime Reconfigurable Architecture N.Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S.K. Nandy   Network-On-Chip Interconnects 2010-IC-24
Alle, Mythri
2010
Design Space Exploration of Systolic Realization of QR Factorization on a Runtime Reconfigurable Platform Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S.K. Nandy  Design Space Exploration 2010-IC-35
Anagnostopoulos, Iraklis
2010
Custom Multi-Threaded Dynamic Memory Management for Multiprocessor System-on-Chip Platforms Sotirios Xydis, Alexandros Bartzas, Iraklis Anagnostopoulos, Dimitrios Soudris, Kiamal Pekmestzi  System-Level Design 2010-IC-15
Arabi, Tawfik
2010
VLSI Challenges to more Energy Efficient Devices Tawfik Arabi  SAMOS X - Keynote 2010-IC-02
Arandi, Samer
2010
Programming Multi-core Architectures Using Data-Flow Techniques Samer Arandi, Paraskevas Evripidou MP-SoC Programming 2010-IC-21
Arlati, Fabio
2010
Designing and Validating Access Policies to Reconfigurable Resources in Multiprocessor Systems on Chip Fabio Arlati, Francesco Bruschi, Donatella Sciuto Special Session on Multicore Architectures for Embedded Systems 2010-IC-49
Arnold, Oliver
2010
Power Aware Heterogeneous MPSoC with Dynamic Task Scheduling and Increased Data Locality for Multiple Applications Oliver Arnold, Gerhard Fettweis System-Level Design 2010-IC-16
Banz, Christian
2010
Real-Time Stereo Vision System using Semi-Global Matching Disparity Estimation: Architecture and FPGA-Implementation Christian Banz, Sebastian Hesselbarth, Holger Flatt, Holger Blume, Peter Pirsch  Image and Video Processing 2010-IC-14
Bartzas, Alexandros
2010
Custom Multi-Threaded Dynamic Memory Management for Multiprocessor System-on-Chip Platforms Sotirios Xydis, Alexandros Bartzas, Iraklis Anagnostopoulos, Dimitrios Soudris, Kiamal Pekmestzi  System-Level Design 2010-IC-15
Becker, Jürgen
2010
Message Passing Interface Support for the Runtime Adaptive Multi-Processor System-on-Chip RAMPSoC Diana Goehringer, Michael Hubner, Laure Hugot-Derville, Jürgen Becker  Special Session on Multicore Architectures for Embedded Systems 2010-IC-48
Bertozzi, Davide
2010
A Library of Dual-Clock FIFOs for Cost-Effective and Flexible MPSoCs Design Alessandro Strano, Daniele Ludovici, Davide Bertozzi Simulation and Modeling 2010-IC-05
Bhattacharyya, Shuvra S.
2010
Efficient Static Buffering to Guarantee Throughput-Optimal FPGA Implementation of Synchronous Dataflow Graphs Hojin Kee, Shuvra S. Bhattacharyya, Jacob Kornerup Profiling and Analysis 2010-IC-19
Biswas, Prasenjit
2010
Design Space Exploration of Systolic Realization of QR Factorization on a Runtime Reconfigurable Platform Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S.K. Nandy  Design Space Exploration 2010-IC-35
Blott, Michaela
2010
Design of a Flexible High-speed FPGA-based Flow Monitor for Next Generation Networks John McGlone, Roger Woods, Alan Marshall, Michaela Blott  Network Processing 2010-IC-07
Blume, Holger
2010
A Fully Programmable FSM-based Processing Engine for Gigabytes/s Header Parsing Konstantin Septinus, Peter Pirsch, Holger Blume, Ulrich Mayer  Network Processing 2010-IC-08
Blume, Holger
2010
Real-Time Stereo Vision System using Semi-Global Matching Disparity Estimation: Architecture and FPGA-Implementation Christian Banz, Sebastian Hesselbarth, Holger Flatt, Holger Blume, Peter Pirsch  Image and Video Processing 2010-IC-14
Bohm, Igor
2010
Cycle-Accurate Performance Modelling in an Ultra-Fast Just-In-Time Dynamic Binary Translation Instruction Set Simulator Igor Bohm, Bjorn Franke, Nigel Topham Simulation and Modeling 2010-IC-03
Bordoloi, Unmesh D.
2010
Design Space Exploration of Instruction Set Customizable MPSoCs for Multimedia Applications Unmesh D. Bordoloi, Huynh Phung Huynh, Tulika Mitra, Samarjit Chakraborty  MP-SoC Programming 2010-IC-23
Bruschi, Francesco
2010
Designing and Validating Access Policies to Reconfigurable Resources in Multiprocessor Systems on Chip Fabio Arlati, Francesco Bruschi, Donatella Sciuto Special Session on Multicore Architectures for Embedded Systems 2010-IC-49
Cabarcas, Felipe
2010
Interleaving Granularity on High Bandwidth Memory Architecture for CMPs Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex Ramirez  Micro-Architecture 2010-IC-33
Carro, Luigi
2010
Monitor-Adapter Coupling for NOC Performance Tuning Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Kastensmidt, Altamiro Susin, Marcio Kreutz   Network-On-Chip Interconnects 2010-IC-26
Carro, Luigi
2010
Introduction to the Special Session on Multicore Architectures for Embedded Systems Luigi Carro, Stephan Wong Special Session on Multicore Architectures for Embedded Systems 2010-IC-44
Chakraborty, Samarjit
2010
Design Space Exploration of Instruction Set Customizable MPSoCs for Multimedia Applications Unmesh D. Bordoloi, Huynh Phung Huynh, Tulika Mitra, Samarjit Chakraborty  MP-SoC Programming 2010-IC-23
Chen, Sao-Jie
2010
ARAL-CR: An Adaptive Reasoning and Learning
Cognitive Radio Platform
Sao-Jie Chen, Pao-Ann Hsiung, Chu Yu, Mao-Hsu Yen, Sakir Sezer, Michael Schulte, Yu-Hen Hu   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-43
Chun, Joon Hwa
2010
CORDIC-Based LMMSE Equalizer for Software Defined Radio Murugappan Senthilvelan, Javier Hormigo, Joon Hwa Chun, Mihai Sima, Daniel Iancu, Michael Schulte, John Glossner   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-40
Ciobanu, Catalin
2010
A Polymorphic Register File for Matrix Operations Catalin Ciobanu, Georgi Kuzmanov, Georgi N. Gaydadjiev, Alex Ramirez  Micro-Architecture 2010-IC-32
Concatto, Caroline
2010
Monitor-Adapter Coupling for NOC Performance Tuning Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Kastensmidt, Altamiro Susin, Marcio Kreutz   Network-On-Chip Interconnects 2010-IC-26
Cornero, Marco
2010
CLI-Based Compilation Flows for the C Language Erven Rohou, Andrea C. Ornstein, Marco Cornero MP-SoC Programming 2010-IC-22
Corporaal, Henk
2010
Fast Huffman Decoding by Exploiting Data Level Parallelism Tim Drijvers, Carlos Alba Pinto, Henk Corporaal, Bart Mesman  Image and Video Processing 2010-IC-13
Corporaal, Henk
2010
Compile-time GPU Memory Access Optimizations Gert-Jan van den Braak, Bart Mesman, Henk Corporaal Compiler Techniques 2010-IC-27
Dave, Dhara
2010
ImpBench Revisited: An Extended Characterization of Implant-Processor Benchmarks Christos Strydis, Dhara Dave, Georgi N. Gaydadjiev Profiling and Analysis 2010-IC-18
de la Lama, Carlos S.
2010
OpenCL-based Design Methodology for Application-Specific Processors Pekka Jääskeläinen, Carlos S. de la Lama, Pablo Huerta, Jarmo Takala  Compiler Techniques 2010-IC-30
de Windt, Jason
2010
On-chip Network Interfaces supporting automatic burst write creation, posted writes and read prefetch Radu Stefan, Jason de Windt, Kees Goossens Network-On-Chip Interconnects 2010-IC-25
Declerck, Jeroen
2010
SDR Platform for 802.11n and 3-GPP LTE  Jeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-42
Dejonghe, Antoine
2010
SDR Platform for 802.11n and 3-GPP LTE  Jeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-42
Drijvers, Tim
2010
Fast Huffman Decoding by Exploiting Data Level Parallelism Tim Drijvers, Carlos Alba Pinto, Henk Corporaal, Bart Mesman  Image and Video Processing 2010-IC-13
Dutta, Avinaba
2010
Enhancements for Variable N-point Streaming FFT/IFFT on REDEFINE, a Runtime Reconfigurable Architecture N.Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S.K. Nandy   Network-On-Chip Interconnects 2010-IC-24
El Mrabti, Amin
2010
Design Environment for the Support of Configurable Network Interfaces in NoC-based Platforms Amin El Mrabti, Frederic Rousseau, Frederic Petrot, Jerome Martin, Romain Lemaire, Emmanuel Vaumorin   Network Processing 2010-IC-10
Etsion, Yoav
2010
Interleaving Granularity on High Bandwidth Memory Architecture for CMPs Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex Ramirez  Micro-Architecture 2010-IC-33
Evripidou, Paraskevas
2010
Programming Multi-core Architectures Using Data-Flow Techniques Samer Arandi, Paraskevas Evripidou MP-SoC Programming 2010-IC-21
Fakhraie, Sied Mehdi
2010
Energy-Aware Design Space Exploration of RegisterFile for Extensible Processors Amir Yazdanbakhsh, Mehdi Kamal, Mostafa E. Salehi, Hamid Noori, Sied Mehdi Fakhraie  Design Space Exploration 2010-IC-36
Falcao, Gabriel
2010
Embedded Multicore Architectures for LDPC Decoding Gabriel Falcao, Leonel Sousa, Vitor Silva Special Session on Multicore Architectures for Embedded Systems 2010-IC-47
Fenacci, Damon
2010
Empirical Evaluation of Data Transformations for Network Infrastructure Applications Damon Fenacci, Bjorn Franke Network Processing 2010-IC-09
Fettweis, Gerhard
2010
Power Aware Heterogeneous MPSoC with Dynamic Task Scheduling and Increased Data Locality for Multiple Applications Oliver Arnold, Gerhard Fettweis System-Level Design 2010-IC-16
Fettweis, Gerhard
2010
Code Generation for a Novel STA Architecture by Using Post-Processing Backend Xiaoyan Jia, Gerhard Fettweis Compiler Techniques 2010-IC-28
Flatt, Holger
2010
Real-Time Stereo Vision System using Semi-Global Matching Disparity Estimation: Architecture and FPGA-Implementation Christian Banz, Sebastian Hesselbarth, Holger Flatt, Holger Blume, Peter Pirsch  Image and Video Processing 2010-IC-14
Franke, Bjorn
2010
Cycle-Accurate Performance Modelling in an Ultra-Fast Just-In-Time Dynamic Binary Translation Instruction Set Simulator Igor Bohm, Bjorn Franke, Nigel Topham Simulation and Modeling 2010-IC-03
Franke, Bjorn
2010
Empirical Evaluation of Data Transformations for Network Infrastructure Applications Damon Fenacci, Bjorn Franke Network Processing 2010-IC-09
Gaydadjiev, Georgi N.
2010
ImpBench Revisited: An Extended Characterization of Implant-Processor Benchmarks Christos Strydis, Dhara Dave, Georgi N. Gaydadjiev Profiling and Analysis 2010-IC-18
Gaydadjiev, Georgi N.
2010
A Polymorphic Register File for Matrix Operations Catalin Ciobanu, Georgi Kuzmanov, Georgi N. Gaydadjiev, Alex Ramirez  Micro-Architecture 2010-IC-32
Gerstlauer, Andreas
2010
A System-Level Synthesis Approach from Formal Application Models to Generic Bus-Based MPSoCs Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubuhr, Jürgen Teich  System-Level Design 2010-IC-17
Gladigau, Jens
2010
A System-Level Synthesis Approach from Formal Application Models to Generic Bus-Based MPSoCs Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubuhr, Jürgen Teich  System-Level Design 2010-IC-17
Glossner, John
2010
Introduction to the Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) John Glossner  Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-38
Glossner, John
2010
CORDIC-Based LMMSE Equalizer for Software Defined Radio Murugappan Senthilvelan, Javier Hormigo, Joon Hwa Chun, Mihai Sima, Daniel Iancu, Michael Schulte, John Glossner   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-40
Goehringer, Diana
2010
Message Passing Interface Support for the Runtime Adaptive Multi-Processor System-on-Chip RAMPSoC Diana Goehringer, Michael Hubner, Laure Hugot-Derville, Jürgen Becker  Special Session on Multicore Architectures for Embedded Systems 2010-IC-48
Goossens, Kees
2010
On-chip Network Interfaces supporting automatic burst write creation, posted writes and read prefetch Radu Stefan, Jason de Windt, Kees Goossens Network-On-Chip Interconnects 2010-IC-25
Gracia-Perez, Daniel
2010
Transparent Sampling Taj Muhammad Khan, Daniel Gracia-Perez, Olivier Temam Simulation and Modeling 2010-IC-06
Haubelt, Christian
2010
A System-Level Synthesis Approach from Formal Application Models to Generic Bus-Based MPSoCs Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubuhr, Jürgen Teich  System-Level Design 2010-IC-17
Hesselbarth, Sebastian
2010
Real-Time Stereo Vision System using Semi-Global Matching Disparity Estimation: Architecture and FPGA-Implementation Christian Banz, Sebastian Hesselbarth, Holger Flatt, Holger Blume, Peter Pirsch  Image and Video Processing 2010-IC-14
Hicks, Michael A.
2010
Towards Scalable I/O on a Many-core Architecture Michael A. Hicks, Hicks Michiel, W. van Tol, Chris R. Jesshope  Special Session on Multicore Architectures for Embedded Systems 2010-IC-46
Hildenbrand, Dietmar
2010
Accelerating High-Level Engineering Computations by Automatic Compilation of Geometric Algebra to Hardware Accelerators Jens Huthmann, Peter Muller, Florian Stock, Dietmar Hildenbrand, Andreas Koch  Compiler Techniques 2010-IC-29
Hollevoet, Lieven
2010
SDR Platform for 802.11n and 3-GPP LTE  Jeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-42
Hormigo, Javier
2010
CORDIC-Based LMMSE Equalizer for Software Defined Radio Murugappan Senthilvelan, Javier Hormigo, Joon Hwa Chun, Mihai Sima, Daniel Iancu, Michael Schulte, John Glossner   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-40
Hsiung, Pao-Ann
2010
ARAL-CR: An Adaptive Reasoning and Learning
Cognitive Radio Platform
Sao-Jie Chen, Pao-Ann Hsiung, Chu Yu, Mao-Hsu Yen, Sakir Sezer, Michael Schulte, Yu-Hen Hu   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-43
Hu, Yu-Hen
2010
ARAL-CR: An Adaptive Reasoning and Learning
Cognitive Radio Platform
Sao-Jie Chen, Pao-Ann Hsiung, Chu Yu, Mao-Hsu Yen, Sakir Sezer, Michael Schulte, Yu-Hen Hu   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-43
Hubner, Michael
2010
Message Passing Interface Support for the Runtime Adaptive Multi-Processor System-on-Chip RAMPSoC Diana Goehringer, Michael Hubner, Laure Hugot-Derville, Jürgen Becker  Special Session on Multicore Architectures for Embedded Systems 2010-IC-48
Huerta, Pablo
2010
OpenCL-based Design Methodology for Application-Specific Processors Pekka Jääskeläinen, Carlos S. de la Lama, Pablo Huerta, Jarmo Takala  Compiler Techniques 2010-IC-30
Hugot-Derville, Laure
2010
Message Passing Interface Support for the Runtime Adaptive Multi-Processor System-on-Chip RAMPSoC Diana Goehringer, Michael Hubner, Laure Hugot-Derville, Jürgen Becker  Special Session on Multicore Architectures for Embedded Systems 2010-IC-48
Huthmann, Jens
2010
Accelerating High-Level Engineering Computations by Automatic Compilation of Geometric Algebra to Hardware Accelerators Jens Huthmann, Peter Muller, Florian Stock, Dietmar Hildenbrand, Andreas Koch  Compiler Techniques 2010-IC-29
Huynh, Huynh Phung
2010
Design Space Exploration of Instruction Set Customizable MPSoCs for Multimedia Applications Unmesh D. Bordoloi, Huynh Phung Huynh, Tulika Mitra, Samarjit Chakraborty  MP-SoC Programming 2010-IC-23
Iancu, Daniel
2010
CORDIC-Based LMMSE Equalizer for Software Defined Radio Murugappan Senthilvelan, Javier Hormigo, Joon Hwa Chun, Mihai Sima, Daniel Iancu, Michael Schulte, John Glossner   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-40
Jääskeläinen, Pekka
2010
OpenCL-based Design Methodology for Application-Specific Processors Pekka Jääskeläinen, Carlos S. de la Lama, Pablo Huerta, Jarmo Takala  Compiler Techniques 2010-IC-30
Janhunen, Janne
2010
A GPU Implementation for two MIMO–OFDM Detectors Teemu Nylanden, Janne Janhunen, Olli Silven, Markku Juntti  Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-39
Jesshope, Chris R.
2010
Towards Scalable I/O on a Many-core Architecture Michael A. Hicks, Hicks Michiel, W. van Tol, Chris R. Jesshope  Special Session on Multicore Architectures for Embedded Systems 2010-IC-46
Jia, Xiaoyan
2010
Code Generation for a Novel STA Architecture by Using Post-Processing Backend Xiaoyan Jia, Gerhard Fettweis Compiler Techniques 2010-IC-28
Juntti, Markku
2010
A GPU Implementation for two MIMO–OFDM Detectors Teemu Nylanden, Janne Janhunen, Olli Silven, Markku Juntti  Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-39
Kamal, Mehdi
2010
Energy-Aware Design Space Exploration of RegisterFile for Extensible Processors Amir Yazdanbakhsh, Mehdi Kamal, Mostafa E. Salehi, Hamid Noori, Sied Mehdi Fakhraie  Design Space Exploration 2010-IC-36
Karlström, Per
2010
Automatic Port and Bus Sizing in NoGAP Per Karlström, Wenbiao Zhou, Dake Liu Micro-Architecture 2010-IC-34
Kastensmidt, Fernanda
2010
Monitor-Adapter Coupling for NOC Performance Tuning Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Kastensmidt, Altamiro Susin, Marcio Kreutz   Network-On-Chip Interconnects 2010-IC-26
Kee, Hojin
2010
Efficient Static Buffering to Guarantee Throughput-Optimal FPGA Implementation of Synchronous Dataflow Graphs Hojin Kee, Shuvra S. Bhattacharyya, Jacob Kornerup Profiling and Analysis 2010-IC-19
Khan, Taj Muhammad
2010
Transparent Sampling Taj Muhammad Khan, Daniel Gracia-Perez, Olivier Temam Simulation and Modeling 2010-IC-06
Koch, Andreas
2010
Accelerating High-Level Engineering Computations by Automatic Compilation of Geometric Algebra to Hardware Accelerators Jens Huthmann, Peter Muller, Florian Stock, Dietmar Hildenbrand, Andreas Koch  Compiler Techniques 2010-IC-29
Kologeski, Anelise
2010
Monitor-Adapter Coupling for NOC Performance Tuning Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Kastensmidt, Altamiro Susin, Marcio Kreutz   Network-On-Chip Interconnects 2010-IC-26
Kornerup, Jacob
2010
Efficient Static Buffering to Guarantee Throughput-Optimal FPGA Implementation of Synchronous Dataflow Graphs Hojin Kee, Shuvra S. Bhattacharyya, Jacob Kornerup Profiling and Analysis 2010-IC-19
Kreutz, Marcio
2010
Monitor-Adapter Coupling for NOC Performance Tuning Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Kastensmidt, Altamiro Susin, Marcio Kreutz   Network-On-Chip Interconnects 2010-IC-26
Kuzmanov, Georgi
2010
An Efficient Realization of Forward Integer Transform in H.264/AVC Intra-frame Encoder Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov Image and Video Processing 2010-IC-11
Kuzmanov, Georgi
2010
A Polymorphic Register File for Matrix Operations Catalin Ciobanu, Georgi Kuzmanov, Georgi N. Gaydadjiev, Alex Ramirez  Micro-Architecture 2010-IC-32
Lemaire, Romain
2010
Design Environment for the Support of Configurable Network Interfaces in NoC-based Platforms Amin El Mrabti, Frederic Rousseau, Frederic Petrot, Jerome Martin, Romain Lemaire, Emmanuel Vaumorin   Network Processing 2010-IC-10
Liu, Dake
2010
Automatic Port and Bus Sizing in NoGAP Per Karlström, Wenbiao Zhou, Dake Liu Micro-Architecture 2010-IC-34
Ludovici, Daniele
2010
A Library of Dual-Clock FIFOs for Cost-Effective and Flexible MPSoCs Design Alessandro Strano, Daniele Ludovici, Davide Bertozzi Simulation and Modeling 2010-IC-05
Marref, Amine
2010
Compositional Timing Analysis Amine Marref  Profiling and Analysis 2010-IC-20
Marshall, Alan
2010
Design of a Flexible High-speed FPGA-based Flow Monitor for Next Generation Networks John McGlone, Roger Woods, Alan Marshall, Michaela Blott  Network Processing 2010-IC-07
Martin, Jerome
2010
Design Environment for the Support of Configurable Network Interfaces in NoC-based Platforms Amin El Mrabti, Frederic Rousseau, Frederic Petrot, Jerome Martin, Romain Lemaire, Emmanuel Vaumorin   Network Processing 2010-IC-10
Matos, Debora
2010
Monitor-Adapter Coupling for NOC Performance Tuning Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Kastensmidt, Altamiro Susin, Marcio Kreutz   Network-On-Chip Interconnects 2010-IC-26
Mayer, Ulrich
2010
A Fully Programmable FSM-based Processing Engine for Gigabytes/s Header Parsing Konstantin Septinus, Peter Pirsch, Holger Blume, Ulrich Mayer  Network Processing 2010-IC-08
McGlone, John
2010
Design of a Flexible High-speed FPGA-based Flow Monitor for Next Generation Networks John McGlone, Roger Woods, Alan Marshall, Michaela Blott  Network Processing 2010-IC-07
Mesman, Bart
2010
Fast Huffman Decoding by Exploiting Data Level Parallelism Tim Drijvers, Carlos Alba Pinto, Henk Corporaal, Bart Mesman  Image and Video Processing 2010-IC-13
Mesman, Bart 
2010
Compile-time GPU Memory Access Optimizations Gert-Jan van den Braak, Bart Mesman, Henk Corporaal Compiler Techniques 2010-IC-27
Michiel, Hicks
2010
Towards Scalable I/O on a Many-core Architecture Michael A. Hicks, Hicks Michiel, W. van Tol, Chris R. Jesshope  Special Session on Multicore Architectures for Embedded Systems 2010-IC-46
Mitra, Tulika
2010
Design Space Exploration of Instruction Set Customizable MPSoCs for Multimedia Applications Unmesh D. Bordoloi, Huynh Phung Huynh, Tulika Mitra, Samarjit Chakraborty  MP-SoC Programming 2010-IC-23
Mudge, Trevor
2010
Technologies for Reducing Power Trevor Mudge  SAMOS X - Keynote 2010-IC-01
Muller, Peter
2010
Accelerating High-Level Engineering Computations by Automatic Compilation of Geometric Algebra to Hardware Accelerators Jens Huthmann, Peter Muller, Florian Stock, Dietmar Hildenbrand, Andreas Koch  Compiler Techniques 2010-IC-29
Nadeem, Muhammad
2010
An Efficient Realization of Forward Integer Transform in H.264/AVC Intra-frame Encoder Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov Image and Video Processing 2010-IC-11
Nadezhkin, Dmitry
2010
Identifying Communication Models in Process Networks derived from Weakly Dynamic Programs Dmitry Nadezhkin, Todor Stefanov Special Session on Multicore Architectures for Embedded Systems 2010-IC-50
Naessens, Frederik
2010
SDR Platform for 802.11n and 3-GPP LTE  Jeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-42
Nandy, S.K.
2010
Enhancements for Variable N-point Streaming FFT/IFFT on REDEFINE, a Runtime Reconfigurable Architecture N.Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S.K. Nandy   Network-On-Chip Interconnects 2010-IC-24
Nandy, S.K.
2010
Design Space Exploration of Systolic Realization of QR Factorization on a Runtime Reconfigurable Platform Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S.K. Nandy  Design Space Exploration 2010-IC-35
Negi, Anurag
2010
LV*: A Low Complexity Lazy Versioning HTM Infrastructure Anurag Negi, M. M. Waliullah, Per Stenstrom Micro-Architecture 2010-IC-31
Noori, Hamid
2010
Energy-Aware Design Space Exploration of RegisterFile for Extensible Processors Amir Yazdanbakhsh, Mehdi Kamal, Mostafa E. Salehi, Hamid Noori, Sied Mehdi Fakhraie  Design Space Exploration 2010-IC-36
Nylanden, Teemu
2010
A GPU Implementation for two MIMO–OFDM Detectors Teemu Nylanden, Janne Janhunen, Olli Silven, Markku Juntti  Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-39
Ornstein, Andrea C.
2010
CLI-Based Compilation Flows for the C Language Erven Rohou, Andrea C. Ornstein, Marco Cornero MP-SoC Programming 2010-IC-22
Pekmestzi, Kiamal
2010
Custom Multi-Threaded Dynamic Memory Management for Multiprocessor System-on-Chip Platforms Sotirios Xydis, Alexandros Bartzas, Iraklis Anagnostopoulos, Dimitrios Soudris, Kiamal Pekmestzi  System-Level Design 2010-IC-15
Petrot, Frederic
2010
Design Environment for the Support of Configurable Network Interfaces in NoC-based Platforms Amin El Mrabti, Frederic Rousseau, Frederic Petrot, Jerome Martin, Romain Lemaire, Emmanuel Vaumorin   Network Processing 2010-IC-10
Pimentel, Andy D.
2010
A Trace-based Scenario Database for High-level Simulation of Multimedia MP-SoCs Peter van Stralen, Andy D. Pimentel Simulation and Modeling 2010-IC-04
Pinto, Carlos Alba
2010
Fast Huffman Decoding by Exploiting Data Level Parallelism Tim Drijvers, Carlos Alba Pinto, Henk Corporaal, Bart Mesman  Image and Video Processing 2010-IC-13
Pirsch, Peter
2010
A Fully Programmable FSM-based Processing Engine for Gigabytes/s Header Parsing Konstantin Septinus, Peter Pirsch, Holger Blume, Ulrich Mayer  Network Processing 2010-IC-08
Pirsch, Peter
2010
Real-Time Stereo Vision System using Semi-Global Matching Disparity Estimation: Architecture and FPGA-Implementation Christian Banz, Sebastian Hesselbarth, Holger Flatt, Holger Blume, Peter Pirsch  Image and Video Processing 2010-IC-14
Prasadarao, M.
2010
Enhancements for Variable N-point Streaming FFT/IFFT on REDEFINE, a Runtime Reconfigurable Architecture N.Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S.K. Nandy   Network-On-Chip Interconnects 2010-IC-24
Prashank, N.Thambi
2010
Enhancements for Variable N-point Streaming FFT/IFFT on REDEFINE, a Runtime Reconfigurable Architecture N.Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S.K. Nandy   Network-On-Chip Interconnects 2010-IC-24
Raghavan, Praveen
2010
SDR Platform for 802.11n and 3-GPP LTE  Jeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-42
Ramirez, Alex
2010
A Polymorphic Register File for Matrix Operations Catalin Ciobanu, Georgi Kuzmanov, Georgi N. Gaydadjiev, Alex Ramirez  Micro-Architecture 2010-IC-32
Ramirez, Alex
2010
Interleaving Granularity on High Bandwidth Memory Architecture for CMPs Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex Ramirez  Micro-Architecture 2010-IC-33
Rico, Alejandro
2010
Interleaving Granularity on High Bandwidth Memory Architecture for CMPs Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex Ramirez  Micro-Architecture 2010-IC-33
Rintaluoma, Tero
2010
SIMD Performance in Software Based Mobile Video Coding Tero Rintaluoma, Olli Silven Image and Video Processing 2010-IC-12
Rohou, Erven
2010
CLI-Based Compilation Flows for the C Language Erven Rohou, Andrea C. Ornstein, Marco Cornero MP-SoC Programming 2010-IC-22
Rousseau, Frederic
2010
Design Environment for the Support of Configurable Network Interfaces in NoC-based Platforms Amin El Mrabti, Frederic Rousseau, Frederic Petrot, Jerome Martin, Romain Lemaire, Emmanuel Vaumorin   Network Processing 2010-IC-10
Salehi, Mostafa E.
2010
Energy-Aware Design Space Exploration of RegisterFile for Extensible Processors Amir Yazdanbakhsh, Mehdi Kamal, Mostafa E. Salehi, Hamid Noori, Sied Mehdi Fakhraie  Design Space Exploration 2010-IC-36
Schröder, Hartmut
2010
On the Scalability of SIMD Processing for Software Defined Radio Algorithms Peter Westermann, Hartmut Schröder Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-41
Schulte, Michael
2010
CORDIC-Based LMMSE Equalizer for Software Defined Radio Murugappan Senthilvelan, Javier Hormigo, Joon Hwa Chun, Mihai Sima, Daniel Iancu, Michael Schulte, John Glossner   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-40
Schulte, Michael
2010
ARAL-CR: An Adaptive Reasoning and Learning
Cognitive Radio Platform
Sao-Jie Chen, Pao-Ann Hsiung, Chu Yu, Mao-Hsu Yen, Sakir Sezer, Michael Schulte, Yu-Hen Hu   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-43
Sciuto, Donatella
2010
Designing and Validating Access Policies to Reconfigurable Resources in Multiprocessor Systems on Chip Fabio Arlati, Francesco Bruschi, Donatella Sciuto Special Session on Multicore Architectures for Embedded Systems 2010-IC-49
Senthilvelan, Murugappan
2010
CORDIC-Based LMMSE Equalizer for Software Defined Radio Murugappan Senthilvelan, Javier Hormigo, Joon Hwa Chun, Mihai Sima, Daniel Iancu, Michael Schulte, John Glossner   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-40
Septinus, Konstantin
2010
A Fully Programmable FSM-based Processing Engine for Gigabytes/s Header Parsing Konstantin Septinus, Peter Pirsch, Holger Blume, Ulrich Mayer  Network Processing 2010-IC-08
Sezer, Sakir
2010
ARAL-CR: An Adaptive Reasoning and Learning
Cognitive Radio Platform
Sao-Jie Chen, Pao-Ann Hsiung, Chu Yu, Mao-Hsu Yen, Sakir Sezer, Michael Schulte, Yu-Hen Hu   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-43
Silva, Vitor
2010
Embedded Multicore Architectures for LDPC Decoding Gabriel Falcao, Leonel Sousa, Vitor Silva Special Session on Multicore Architectures for Embedded Systems 2010-IC-47
Silven, Olli
2010
SIMD Performance in Software Based Mobile Video Coding Tero Rintaluoma, Olli Silven Image and Video Processing 2010-IC-12
Silven, Olli
2010
A GPU Implementation for two MIMO–OFDM Detectors Teemu Nylanden, Janne Janhunen, Olli Silven, Markku Juntti  Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-39
Sima, Mihai
2010
CORDIC-Based LMMSE Equalizer for Software Defined Radio Murugappan Senthilvelan, Javier Hormigo, Joon Hwa Chun, Mihai Sima, Daniel Iancu, Michael Schulte, John Glossner   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-40
Soudris, Dimitrios
2010
Custom Multi-Threaded Dynamic Memory Management for Multiprocessor System-on-Chip Platforms Sotirios Xydis, Alexandros Bartzas, Iraklis Anagnostopoulos, Dimitrios Soudris, Kiamal Pekmestzi  System-Level Design 2010-IC-15
Sousa, Leonel
2010
Embedded Multicore Architectures for LDPC Decoding Gabriel Falcao, Leonel Sousa, Vitor Silva Special Session on Multicore Architectures for Embedded Systems 2010-IC-47
Stefan, Radu
2010
On-chip Network Interfaces supporting automatic burst write creation, posted writes and read prefetch Radu Stefan, Jason de Windt, Kees Goossens Network-On-Chip Interconnects 2010-IC-25
Stefanov, Todor
2010
Identifying Communication Models in Process Networks derived from Weakly Dynamic Programs Dmitry Nadezhkin, Todor Stefanov Special Session on Multicore Architectures for Embedded Systems 2010-IC-50
Stenstrom, Per
2010
LV*: A Low Complexity Lazy Versioning HTM Infrastructure Anurag Negi, M. M. Waliullah, Per Stenstrom Micro-Architecture 2010-IC-31
Stock, Florian
2010
Accelerating High-Level Engineering Computations by Automatic Compilation of Geometric Algebra to Hardware Accelerators Jens Huthmann, Peter Muller, Florian Stock, Dietmar Hildenbrand, Andreas Koch  Compiler Techniques 2010-IC-29
Strano, Alessandro
2010
A Library of Dual-Clock FIFOs for Cost-Effective and Flexible MPSoCs Design Alessandro Strano, Daniele Ludovici, Davide Bertozzi Simulation and Modeling 2010-IC-05
Streubuhr, Martin
2010
A System-Level Synthesis Approach from Formal Application Models to Generic Bus-Based MPSoCs Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubuhr, Jürgen Teich  System-Level Design 2010-IC-17
Strydis, Christos
2010
ImpBench Revisited: An Extended Characterization of Implant-Processor Benchmarks Christos Strydis, Dhara Dave, Georgi N. Gaydadjiev Profiling and Analysis 2010-IC-18
Susin, Altamiro
2010
Monitor-Adapter Coupling for NOC Performance Tuning Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Kastensmidt, Altamiro Susin, Marcio Kreutz   Network-On-Chip Interconnects 2010-IC-26
Takala, Jarmo
2010
OpenCL-based Design Methodology for Application-Specific Processors Pekka Jääskeläinen, Carlos S. de la Lama, Pablo Huerta, Jarmo Takala  Compiler Techniques 2010-IC-30
Teich, Jürgen
2010
A System-Level Synthesis Approach from Formal Application Models to Generic Bus-Based MPSoCs Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubuhr, Jürgen Teich  System-Level Design 2010-IC-17
Temam, Olivier
2010
Transparent Sampling Taj Muhammad Khan, Daniel Gracia-Perez, Olivier Temam Simulation and Modeling 2010-IC-06
Topham, Nigel
2010
Cycle-Accurate Performance Modelling in an Ultra-Fast Just-In-Time Dynamic Binary Translation Instruction Set Simulator Igor Bohm, Bjorn Franke, Nigel Topham Simulation and Modeling 2010-IC-03
Topham, Nigel
2010
Exploring the Unified Design-Space of Custom-Instruction Selection and Resource Sharing Marcela Zuluaga, Nigel Topham Design Space Exploration 2010-IC-37
van den Braak, Gert-Jan
2010
Compile-time GPU Memory Access Optimizations Gert-Jan van den Braak, Bart Mesman, Henk Corporaal Compiler Techniques 2010-IC-27
Van der Perre, Liesbet
2010
SDR Platform for 802.11n and 3-GPP LTE  Jeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-42
van Stralen, Peter
2010
A Trace-based Scenario Database for High-level Simulation of Multimedia MP-SoCs Peter van Stralen, Andy D. Pimentel Simulation and Modeling 2010-IC-04
van Tol, W.
2010
Towards Scalable I/O on a Many-core Architecture Michael A. Hicks, Hicks Michiel, W. van Tol, Chris R. Jesshope  Special Session on Multicore Architectures for Embedded Systems 2010-IC-46
Vander Aa, Tom
2010
SDR Platform for 802.11n and 3-GPP LTE  Jeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-42
Varadarajan, Keshavan
2010
Enhancements for Variable N-point Streaming FFT/IFFT on REDEFINE, a Runtime Reconfigurable Architecture N.Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S.K. Nandy   Network-On-Chip Interconnects 2010-IC-24
Varadarajan, Keshavan
2010
Design Space Exploration of Systolic Realization of QR Factorization on a Runtime Reconfigurable Platform Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S.K. Nandy  Design Space Exploration 2010-IC-35
Vaumorin, Emmanuel
2010
Design Environment for the Support of Configurable Network Interfaces in NoC-based Platforms Amin El Mrabti, Frederic Rousseau, Frederic Petrot, Jerome Martin, Romain Lemaire, Emmanuel Vaumorin   Network Processing 2010-IC-10
Waliullah, M. M.
2010
LV*: A Low Complexity Lazy Versioning HTM Infrastructure Anurag Negi, M. M. Waliullah, Per Stenstrom Micro-Architecture 2010-IC-31
Westermann, Peter
2010
On the Scalability of SIMD Processing for Software Defined Radio Algorithms Peter Westermann, Hartmut Schröder Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-41
Wong, Stephan
2010
An Efficient Realization of Forward Integer Transform in H.264/AVC Intra-frame Encoder Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov Image and Video Processing 2010-IC-11
Wong, Stephan
2010
Introduction to the Special Session on Multicore Architectures for Embedded Systems Luigi Carro, Stephan Wong Special Session on Multicore Architectures for Embedded Systems 2010-IC-44
Woods, Roger
2010
Design of a Flexible High-speed FPGA-based Flow Monitor for Next Generation Networks John McGlone, Roger Woods, Alan Marshall, Michaela Blott  Network Processing 2010-IC-07
Xydis, Sotirios
2010
Custom Multi-Threaded Dynamic Memory Management for Multiprocessor System-on-Chip Platforms Sotirios Xydis, Alexandros Bartzas, Iraklis Anagnostopoulos, Dimitrios Soudris, Kiamal Pekmestzi  System-Level Design 2010-IC-15
Yazdanbakhsh, Amir
2010
Energy-Aware Design Space Exploration of RegisterFile for Extensible Processors Amir Yazdanbakhsh, Mehdi Kamal, Mostafa E. Salehi, Hamid Noori, Sied Mehdi Fakhraie  Design Space Exploration 2010-IC-36
Yen, Mao-Hsu
2010
ARAL-CR: An Adaptive Reasoning and Learning
Cognitive Radio Platform
Sao-Jie Chen, Pao-Ann Hsiung, Chu Yu, Mao-Hsu Yen, Sakir Sezer, Michael Schulte, Yu-Hen Hu   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-43
Ykman-Couvreur, Ch.
2010
Exploration Framework for Run-Time Resource Management of Embedded Multi-Core Platforms Ch. Ykman-Couvreur  Special Session on Multicore Architectures for Embedded Systems 2010-IC-45
Yu, Chu
2010
ARAL-CR: An Adaptive Reasoning and Learning
Cognitive Radio Platform
Sao-Jie Chen, Pao-Ann Hsiung, Chu Yu, Mao-Hsu Yen, Sakir Sezer, Michael Schulte, Yu-Hen Hu   Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR) 2010-IC-43
Zhou, Wenbiao
2010
Automatic Port and Bus Sizing in NoGAP Per Karlström, Wenbiao Zhou, Dake Liu Micro-Architecture 2010-IC-34
Zuluaga, Marcela
2010
Exploring the Unified Design-Space of Custom-Instruction Selection and Resource Sharing Marcela Zuluaga, Nigel Topham Design Space Exploration 2010-IC-37
Adeva, Esther P.
2011
Scalable ASIP Implementation and Parallelization of a MIMO Sphere Detector Esther P. Adeva, Bjorn Mennenga, Gerhard Fettweis Memory and Communication Strategies 2011-IC-31
Al-Dujaily, Ra’ed
2011
On-Chip Dynamic Programming Networks Using 3D-TSV Integration Ra’ed Al-Dujaily, Terrence Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alex Yakovlev, Chi-Sang Poon SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-43
Almer, Oscar
2011
Scalable Multi-Core Simulation Using Parallel Dynamic Binary Translation Oscar Almer, Igor Bohm, Tobias Edler von Koch, Bjorn Franke, Stephen Kyle, Volker Seeker   Simulation and Modeling 2011-IC-26
Alvanos, Michail
2011
Task-based Parallel H.264 Video Encoding for Explicit Communication Architectures Michail Alvanos, George Tzenakis, Dimitrios S. Nikolopoulos, Angelos Bilas  Image and Video Processing 2011-IC-29
Arnold, Oliver
2011
On the Impact of Dynamic Task Scheduling in Heterogeneous MPSoCs Oliver Arnold, Gerhard Fettweis Multicore Programming 2011-IC-05
Asher, Yosi Ben
2011
Optimizing Wait-States in the Synthesis of Memory References with Unpredictable Latencies Yosi Ben Asher, Ron Meldiner, Nadav Rotem Memory and Communication Strategies 2011-IC-36
Auguin, Michel
2011
A Performance Estimation Flow for Embedded Systems with Mixed Software/Hardware Modeling Joffrey Kriegel, Alain Pegatoquet, Michel Auguin, Florian Broekaert  Simulation and Modeling 2011-IC-24
Banz, Christian
2011
A Hardware Accelerated Configurable ASIP Architecture for Embedded Real-Time Video-Based Driver Assistance Applications Gregor Schewior, Holger Flatt, Carsten Dolar, Christian Banz, Holger Blume  Image and Video Processing 2011-IC-28
Basten, Twan
2011
Integrated Model-Driven Design-Space Exploration for Embedded Systems  Nikola Trcka, Martijn Hendriks, Twan Basten, Marc Geilen, Lou Somers    SPECIAL SESSION 2: What's next for ESL 2011-IC-47
Basten, Twan
2011
Scenario-Aware Dataflow: Modeling, Analysis and Implementation of Dynamic Applications Sander Stuijk, Marc Geilen, Bart Theelen, Twan Basten    SPECIAL SESSION 3: Adaptive Systems 2011-IC-56
Becker, Jürgen
2011
Architecture Design Space Exploration of Run-Time Scalable Issue-Width Processors Ralf Koenig, Timo Stripf, Jan Heisswolf, Jürgen Becker  Design Space Exploration 2011-IC-12
Becker, Jürgen
2011
A Novel ADL-based Compiler-Centric Software Framework for Reconfigurable Mixed-ISA Processors Timo Stripf, Ralf Koenig, Jürgen Becker Simulation and Modeling 2011-IC-22
Becker, Jürgen
2011
Heterogeneous and Runtime Parameterizable Star-Wheels Network-on-Chip Diana Goehringer, Oliver Oey, Michael Hubner, Jürgen Becker    SPECIAL SESSION 3: Adaptive Systems 2011-IC-53
Bekooij, Marco J.G.
2011
Mapping of Modal Applications given Throughput and Latency Constraints Stefan J. Geuns, Joost P.H.M. Hausmans, Marco J.G. Bekooij SPECIAL SESSION 3: Adaptive Systems 2011-IC-52
Bertels, Koen
2011
High Level Quantitative Hardware Prediction Modeling using Statistical methods Roel Meeuws, Carlo Galuzzi, Koen Bertels Simulation and Modeling 2011-IC-20
Bhattacharyya, Shuvra S.
2011
Methods for Design and Implementation of Dynamic Signal Processing Systems Shuvra S. Bhattacharyya  SAMOS XI - Keynote 2011-IC-01
Bilas, Angelos
2011
Task-based Parallel H.264 Video Encoding for Explicit Communication Architectures Michail Alvanos, George Tzenakis, Dimitrios S. Nikolopoulos, Angelos Bilas  Image and Video Processing 2011-IC-29
Blume, Holger
2011
A Hardware Accelerated Configurable ASIP Architecture for Embedded Real-Time Video-Based Driver Assistance Applications Gregor Schewior, Holger Flatt, Carsten Dolar, Christian Banz, Holger Blume  Image and Video Processing 2011-IC-28
Blume, Holger
2011
Using SDRAMs for two-dimensional accesses of long 2n × 2m-point FFTs and transposing Stefan Langemeyer, Peter Pirsch, Holger Blume Memory and Communication Strategies 2011-IC-32
Bohm, Igor
2011
Scalable Multi-Core Simulation Using Parallel Dynamic Binary Translation Oscar Almer, Igor Bohm, Tobias Edler von Koch, Bjorn Franke, Stephen Kyle, Volker Seeker   Simulation and Modeling 2011-IC-26
Borodin, Demid
2011
Functional Unit Sharing Between Stacked Processors in 3D Integrated Systems Demid Borodin, Winston Siauw, Sorin Dan Cotofana  SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-42
Broekaert, Florian
2011
A Performance Estimation Flow for Embedded Systems with Mixed Software/Hardware Modeling Joffrey Kriegel, Alain Pegatoquet, Michel Auguin, Florian Broekaert  Simulation and Modeling 2011-IC-24
Bruschi, Francesco
2011
On-Chip Network Resource Management Design and Validation Francesco Bruschi, Antonio Miele, Vincenzo Rana Memory and Communication Strategies 2011-IC-33
Cabarcas, Felipe
2011
Breaking the Bandwidth Wall in Chip Multiprocessors Augusto Vega, Felipe Cabarcas, Alex Ramirez, Mateo Valero  Memory and Communication Strategies 2011-IC-34
Cahill, Kurtis D.
2011
ADL-Based Specification of Implementation Styles for Functional Simulators David A. Penry, Kurtis D. Cahill Simulation and Modeling 2011-IC-23
Cancare, Fabio
2011
Dedicated Hardware Accelerators for the Epistatic Analysis of Human Genetic Data Fabio Cancare, Alessandro Marin, Donatella Sciuto Accelerators 2011-IC-15
Castrillon, Jeronimo
2011
Trends in Embedded Software Synthesis Jeronimo Castrillon, Weihua Sheng, Rainer Leupers SPECIAL SESSION 2: What's next for ESL 2011-IC-48
Chang, Daniel W.
2011
Analyzing the Performance and Energy Impact of 3D Memory Integration on Embedded DSPs Daniel W. Chang, Nam S. Kim, Michael Schulte  SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-41
Corporaal, Henk
2011
Skeleton-based Automatic Parallelization of Image Processing Algorithms for GPUs Cedric Nugteren, Henk Corporaal, Bart Mesman Multicore Programming 2011-IC-06
Corporaal, Henk
2011
Distributed Resource Management for Concurrent Execution of Multimedia Applications on MPSoC Platforms Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal  Accelerators 2011-IC-19
Corporaal, Henk
2011
MOVE-Pro: a Low Power and High Code Density TTA Architecture Yifan He, Dongrui She, Bart Mesman, Henk Corporaal  Memory and Communication Strategies 2011-IC-39
Cotofana, Sorin Dan
2011
Functional Unit Sharing Between Stacked Processors in 3D Integrated Systems Demid Borodin, Winston Siauw, Sorin Dan Cotofana  SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-42
Davis, W. Rhett
2011
3D Specific Systems Design and CAD Paul D. Franzon, Thor Thorolfsson, W. Rhett Davis, Samson Melamed SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-44
de la Lama, Carlos S.
2011
TCEMC: A Co-Design Flow for Application-Specific Multicores Pekka Jääskeläinen, Erno Salminen, Carlos S. de la Lama, Jarmo Takala, Jose Ignacio Martinez  Design Space Exploration 2011-IC-13
Diamantopoulos, Dionisios
2011
Thermal optimization for micro-architectures through selective block replication Dionisios Diamantopoulos, Kostas Siozios, Sotirios Xydis, Dimitrios Soudris  Energy-Aware and Low-Power Designs 2011-IC-10
Dias, Tiago
2011
High Throughput and Scalable Architecture for Unified Transform Coding in Embedded H.264/AVC Video Coding Systems Tiago Dias, Sebastian Lopez, Nuno Roma, Leonel Sousa  Image and Video Processing 2011-IC-30
Dolar, Carsten
2011
A Hardware Accelerated Configurable ASIP Architecture for Embedded Real-Time Video-Based Driver Assistance Applications Gregor Schewior, Holger Flatt, Carsten Dolar, Christian Banz, Holger Blume  Image and Video Processing 2011-IC-28
Ernst, Rolf
2011
Admission Control and Self-Configuration in the EPOC Framework Steffen Stein, Moritz Neukirchner, Rolf Ernst SPECIAL SESSION 3: Adaptive Systems 2011-IC-51
Fahmy, Sherif
2011
On STM Concurrency Control for Multicore Embedded Real-Time Software Sherif Fahmy, Binoy Ravindran Multicore Programming 2011-IC-03
Fettweis, Gerhard
2011
On the Impact of Dynamic Task Scheduling in Heterogeneous MPSoCs Oliver Arnold, Gerhard Fettweis Multicore Programming 2011-IC-05
Fettweis, Gerhard
2011
Scalable ASIP Implementation and Parallelization of a MIMO Sphere Detector Esther P. Adeva, Bjorn Mennenga, Gerhard Fettweis Memory and Communication Strategies 2011-IC-31
Flatt, Holger
2011
A Hardware Accelerated Configurable ASIP Architecture for Embedded Real-Time Video-Based Driver Assistance Applications Gregor Schewior, Holger Flatt, Carsten Dolar, Christian Banz, Holger Blume  Image and Video Processing 2011-IC-28
Franke, Bjorn
2011
Scalable Multi-Core Simulation Using Parallel Dynamic Binary Translation Oscar Almer, Igor Bohm, Tobias Edler von Koch, Bjorn Franke, Stephen Kyle, Volker Seeker   Simulation and Modeling 2011-IC-26
Franzon, Paul D.
2011
3D Specific Systems Design and CAD Paul D. Franzon, Thor Thorolfsson, W. Rhett Davis, Samson Melamed SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-44
Galuzzi, Carlo
2011
High Level Quantitative Hardware Prediction Modeling using Statistical methods Roel Meeuws, Carlo Galuzzi, Koen Bertels Simulation and Modeling 2011-IC-20
Gaydadjiev, Georgi N.
2011
Vector Processor Customization for FFT Bogdan Spinean, Georgi Kuzmanov, Georgi N. Gaydadjiev Accelerators 2011-IC-16
Geilen, Marc
2011
Integrated Model-Driven Design-Space Exploration for Embedded Systems  Nikola Trcka, Martijn Hendriks, Twan Basten, Marc Geilen, Lou Somers    SPECIAL SESSION 2: What's next for ESL 2011-IC-47
Geilen, Marc
2011
Scenario-Aware Dataflow: Modeling, Analysis and Implementation of Dynamic Applications Sander Stuijk, Marc Geilen, Bart Theelen, Twan Basten    SPECIAL SESSION 3: Adaptive Systems 2011-IC-56
Geuns, Stefan J.
2011
Mapping of Modal Applications given Throughput and Latency Constraints Stefan J. Geuns, Joost P.H.M. Hausmans, Marco J.G. Bekooij SPECIAL SESSION 3: Adaptive Systems 2011-IC-52
Goehringer, Diana
2011
Heterogeneous and Runtime Parameterizable Star-Wheels Network-on-Chip Diana Goehringer, Oliver Oey, Michael Hubner, Jürgen Becker    SPECIAL SESSION 3: Adaptive Systems 2011-IC-53
Goossens, Kees
2011
Composable Power Management with Energy and Power Budgets per Application Andrew Nelson, Anca M. Molnos, Kees Goossens     SPECIAL SESSION 3: Adaptive Systems 2011-IC-55
Gruttner, Kim
2011
Challenges of Multi- and Many-Core Architectures for Electronic System-Level Design Kim Gruttner, Philipp A. Hartmann, Wolfgang Nebel     SPECIAL SESSION 2: What's next for ESL 2011-IC-46
Guzma, Vladimír
2011
Instruction Buffer with Limited Control Flow and Loop Nest Support Vladimír Guzma, Teemu Pitkänen, Jarmo Takala Memory and Communication Strategies 2011-IC-35
Ha, Soonhoi
2011
Software Synthesis in the ESL Methodology for Multicore Embedded Systems Soonhoi Ha, Hyunok Oh     SPECIAL SESSION 2: What's next for ESL 2011-IC-49
Hämäläinen, Timo D.
2011
Multicore Communications API (MCAPI) implementation on an FPGA multiprocessor Lauri Matilainen, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen  Memory and Communication Strategies 2011-IC-38
Hännikäinen, Marko
2011
Multicore Communications API (MCAPI) implementation on an FPGA multiprocessor Lauri Matilainen, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen  Memory and Communication Strategies 2011-IC-38
Hannuksela, Jari
2011
FPGA Based Application Specific Processing for Sensor Nodes Teemu Nylanden, Janne Janhunen, Jari Hannuksela, Olli Silven  Accelerators 2011-IC-17
Hartmann, Philipp A.
2011
Challenges of Multi- and Many-Core Architectures for Electronic System-Level Design Kim Gruttner, Philipp A. Hartmann, Wolfgang Nebel     SPECIAL SESSION 2: What's next for ESL 2011-IC-46
Haubelt, Christian
2011
Calibration and Validation of Software Performance Models for Pedestrian Detection Systems Rainer Kiesel, Martin Streubuhr, Christian Haubelt, Otto Lohlein, Jürgen Teich  Simulation and Modeling 2011-IC-25
Haubelt, Christian
2011
Introduction to the Special Session on "What's next for ESL" Christian Haubelt    SPECIAL SESSION 2: What's next for ESL 2011-IC-45
Hausmans, Joost P.H.M.
2011
Mapping of Modal Applications given Throughput and Latency Constraints Stefan J. Geuns, Joost P.H.M. Hausmans, Marco J.G. Bekooij SPECIAL SESSION 3: Adaptive Systems 2011-IC-52
He, Yifan
2011
MOVE-Pro: a Low Power and High Code Density TTA Architecture Yifan He, Dongrui She, Bart Mesman, Henk Corporaal  Memory and Communication Strategies 2011-IC-39
Heisswolf, Jan
2011
Architecture Design Space Exploration of Run-Time Scalable Issue-Width Processors Ralf Koenig, Timo Stripf, Jan Heisswolf, Jürgen Becker  Design Space Exploration 2011-IC-12
Hendriks, Martijn
2011
Integrated Model-Driven Design-Space Exploration for Embedded Systems  Nikola Trcka, Martijn Hendriks, Twan Basten, Marc Geilen, Lou Somers    SPECIAL SESSION 2: What's next for ESL 2011-IC-47
Herkersdorf, Andreas
2011
Accelerating Collective Communication in Message Passing on Manycore System-on-Chip Stefan Wallentowitz, Marcel Meyer, Thomas Wild, Andreas Herkersdorf  Multicore Programming 2011-IC-04
Holmbacka, Simon
2011
Power Proportional Characteristics of an Energy Manager for Web Clusters Simon Holmbacka, Sebastien Lafond, Johan Lilius Energy-Aware and Low-Power Designs 2011-IC-09
Hubner, Michael
2011
Heterogeneous and Runtime Parameterizable Star-Wheels Network-on-Chip Diana Goehringer, Oliver Oey, Michael Hubner, Jürgen Becker    SPECIAL SESSION 3: Adaptive Systems 2011-IC-53
Jääskeläinen, Pekka
2011
TCEMC: A Co-Design Flow for Application-Specific Multicores Pekka Jääskeläinen, Erno Salminen, Carlos S. de la Lama, Jarmo Takala, Jose Ignacio Martinez  Design Space Exploration 2011-IC-13
Janhunen, Janne
2011
FPGA Based Application Specific Processing for Sensor Nodes Teemu Nylanden, Janne Janhunen, Jari Hannuksela, Olli Silven  Accelerators 2011-IC-17
Jones, Timothy M.
2011
Smart Cache: A Self Adaptive Cache Architecture for Energy Efficiency Karthik T. Sundararajan, Timothy M. Jones, Nigel Topham Energy-Aware and Low-Power Designs 2011-IC-08
Kiesel, Rainer
2011
Calibration and Validation of Software Performance Models for Pedestrian Detection Systems Rainer Kiesel, Martin Streubuhr, Christian Haubelt, Otto Lohlein, Jürgen Teich  Simulation and Modeling 2011-IC-25
Kim, Nam S.
2011
Analyzing the Performance and Energy Impact of 3D Memory Integration on Embedded DSPs Daniel W. Chang, Nam S. Kim, Michael Schulte  SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-41
Koenig, Ralf
2011
Architecture Design Space Exploration of Run-Time Scalable Issue-Width Processors Ralf Koenig, Timo Stripf, Jan Heisswolf, Jürgen Becker  Design Space Exploration 2011-IC-12
Koenig, Ralf
2011
A Novel ADL-based Compiler-Centric Software Framework for Reconfigurable Mixed-ISA Processors Timo Stripf, Ralf Koenig, Jürgen Becker Simulation and Modeling 2011-IC-22
Kokkeler, Andre B.J.
2011
Multi-domain transformational design flow for embedded systems Kenneth C. Rovers, Marcel D. van de Burgwal, Jan Kuper, Andre B.J. Kokkeler, Gerard J. M. Smit  Design Space Exploration 2011-IC-14
Kokkeler, Andre B.J.
2011
Adaptive resource allocation for streaming applications Timon D. ter Braak, Hermen A. Toersche, Andre B.J. Kokkeler, Gerard J. M. Smit    SPECIAL SESSION 3: Adaptive Systems 2011-IC-54
Kriegel, Joffrey
2011
A Performance Estimation Flow for Embedded Systems with Mixed Software/Hardware Modeling Joffrey Kriegel, Alain Pegatoquet, Michel Auguin, Florian Broekaert  Simulation and Modeling 2011-IC-24
Kumar, Akash
2011
Distributed Resource Management for Concurrent Execution of Multimedia Applications on MPSoC Platforms Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal  Accelerators 2011-IC-19
Kuper, Jan
2011
Multi-domain transformational design flow for embedded systems Kenneth C. Rovers, Marcel D. van de Burgwal, Jan Kuper, Andre B.J. Kokkeler, Gerard J. M. Smit  Design Space Exploration 2011-IC-14
Kuzmanov, Georgi
2011
Vector Processor Customization for FFT Bogdan Spinean, Georgi Kuzmanov, Georgi N. Gaydadjiev Accelerators 2011-IC-16
Kyle, Stephen
2011
Scalable Multi-Core Simulation Using Parallel Dynamic Binary Translation Oscar Almer, Igor Bohm, Tobias Edler von Koch, Bjorn Franke, Stephen Kyle, Volker Seeker   Simulation and Modeling 2011-IC-26
Lafond, Sebastien
2011
Power Proportional Characteristics of an Energy Manager for Web Clusters Simon Holmbacka, Sebastien Lafond, Johan Lilius Energy-Aware and Low-Power Designs 2011-IC-09
Lam, Kai-Pui
2011
On-Chip Dynamic Programming Networks Using 3D-TSV Integration Ra’ed Al-Dujaily, Terrence Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alex Yakovlev, Chi-Sang Poon SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-43
Langemeyer, Stefan
2011
Using SDRAMs for two-dimensional accesses of long 2n × 2m-point FFTs and transposing Stefan Langemeyer, Peter Pirsch, Holger Blume Memory and Communication Strategies 2011-IC-32
Le Masle, Adrien
2011
Parametrized Hardware Architectures for the Lucas Primality Test Adrien Le Masle, Wayne Luk, Csaba Andras Moritz Accelerators 2011-IC-18
Leupers, Rainer
2011
Trends in Embedded Software Synthesis Jeronimo Castrillon, Weihua Sheng, Rainer Leupers SPECIAL SESSION 2: What's next for ESL 2011-IC-48
Lilius, Johan
2011
Power Proportional Characteristics of an Energy Manager for Web Clusters Simon Holmbacka, Sebastien Lafond, Johan Lilius Energy-Aware and Low-Power Designs 2011-IC-09
Liu, Qiang
2011
Power Adaptive Computing System Design in Energy Harvesting Environment Qiang Liu, Terrence Mak, Junwen Luo, Wayne Luk, Alex Yakovlev  Energy-Aware and Low-Power Designs 2011-IC-07
Lohlein, Otto
2011
Calibration and Validation of Software Performance Models for Pedestrian Detection Systems Rainer Kiesel, Martin Streubuhr, Christian Haubelt, Otto Lohlein, Jürgen Teich  Simulation and Modeling 2011-IC-25
Lopez, Sebastian
2011
High Throughput and Scalable Architecture for Unified Transform Coding in Embedded H.264/AVC Video Coding Systems Tiago Dias, Sebastian Lopez, Nuno Roma, Leonel Sousa  Image and Video Processing 2011-IC-30
Lu, Kun
2011
Removal of Unnecessary Context Switches from the SystemC Simulation Kernel for Fast VP Simulation Kun Lu, Daniel Muller-Gritschneder, Ulf Schlichtmann Simulation and Modeling 2011-IC-21
Luk, Wayne
2011
Power Adaptive Computing System Design in Energy Harvesting Environment Qiang Liu, Terrence Mak, Junwen Luo, Wayne Luk, Alex Yakovlev  Energy-Aware and Low-Power Designs 2011-IC-07
Luk, Wayne
2011
Parametrized Hardware Architectures for the Lucas Primality Test Adrien Le Masle, Wayne Luk, Csaba Andras Moritz Accelerators 2011-IC-18
Luo, Junwen
2011
Power Adaptive Computing System Design in Energy Harvesting Environment Qiang Liu, Terrence Mak, Junwen Luo, Wayne Luk, Alex Yakovlev  Energy-Aware and Low-Power Designs 2011-IC-07
Mak, Terrence
2011
Power Adaptive Computing System Design in Energy Harvesting Environment Qiang Liu, Terrence Mak, Junwen Luo, Wayne Luk, Alex Yakovlev  Energy-Aware and Low-Power Designs 2011-IC-07
Mak, Terrence
2011
On-Chip Dynamic Programming Networks Using 3D-TSV Integration Ra’ed Al-Dujaily, Terrence Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alex Yakovlev, Chi-Sang Poon SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-43
Marin, Alessandro
2011
Dedicated Hardware Accelerators for the Epistatic Analysis of Human Genetic Data Fabio Cancare, Alessandro Marin, Donatella Sciuto Accelerators 2011-IC-15
Marref, Amine
2011
Fully-Automatic Derivation of Exact Program-Flow Constraints for a TighterWorst-Case Execution-Time Analysis Amine Marref  Simulation and Modeling 2011-IC-27
Martinez, Jose Ignacio
2011
TCEMC: A Co-Design Flow for Application-Specific Multicores Pekka Jääskeläinen, Erno Salminen, Carlos S. de la Lama, Jarmo Takala, Jose Ignacio Martinez  Design Space Exploration 2011-IC-13
Matilainen, Lauri
2011
Multicore Communications API (MCAPI) implementation on an FPGA multiprocessor Lauri Matilainen, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen  Memory and Communication Strategies 2011-IC-38
McAllister, John
2011
A Kernel Interleaved Scheduling Method for Streaming Applications on Soft-core Vector Processors Chengwei Zheng, John McAllister, Yun Wu Memory and Communication Strategies 2011-IC-37
Meeuws, Roel
2011
High Level Quantitative Hardware Prediction Modeling using Statistical methods Roel Meeuws, Carlo Galuzzi, Koen Bertels Simulation and Modeling 2011-IC-20
Melamed, Samson
2011
3D Specific Systems Design and CAD Paul D. Franzon, Thor Thorolfsson, W. Rhett Davis, Samson Melamed SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-44
Meldiner, Ron
2011
Optimizing Wait-States in the Synthesis of Memory References with Unpredictable Latencies Yosi Ben Asher, Ron Meldiner, Nadav Rotem Memory and Communication Strategies 2011-IC-36
Meng, Yicong
2011
On-Chip Dynamic Programming Networks Using 3D-TSV Integration Ra’ed Al-Dujaily, Terrence Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alex Yakovlev, Chi-Sang Poon SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-43
Mennenga, Bjorn
2011
Scalable ASIP Implementation and Parallelization of a MIMO Sphere Detector Esther P. Adeva, Bjorn Mennenga, Gerhard Fettweis Memory and Communication Strategies 2011-IC-31
Mesman, Bart
2011
Skeleton-based Automatic Parallelization of Image Processing Algorithms for GPUs Cedric Nugteren, Henk Corporaal, Bart Mesman Multicore Programming 2011-IC-06
Mesman, Bart
2011
Distributed Resource Management for Concurrent Execution of Multimedia Applications on MPSoC Platforms Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal  Accelerators 2011-IC-19
Mesman, Bart
2011
MOVE-Pro: a Low Power and High Code Density TTA Architecture Yifan He, Dongrui She, Bart Mesman, Henk Corporaal  Memory and Communication Strategies 2011-IC-39
Meyer, Marcel
2011
Accelerating Collective Communication in Message Passing on Manycore System-on-Chip Stefan Wallentowitz, Marcel Meyer, Thomas Wild, Andreas Herkersdorf  Multicore Programming 2011-IC-04
Miele, Antonio
2011
On-Chip Network Resource Management Design and Validation Francesco Bruschi, Antonio Miele, Vincenzo Rana Memory and Communication Strategies 2011-IC-33
Molnos, Anca M.
2011
Composable Power Management with Energy and Power Budgets per Application Andrew Nelson, Anca M. Molnos, Kees Goossens     SPECIAL SESSION 3: Adaptive Systems 2011-IC-55
Moritz, Csaba Andras
2011
Parametrized Hardware Architectures for the Lucas Primality Test Adrien Le Masle, Wayne Luk, Csaba Andras Moritz Accelerators 2011-IC-18
Muller-Gritschneder, Daniel
2011
Removal of Unnecessary Context Switches from the SystemC Simulation Kernel for Fast VP Simulation Kun Lu, Daniel Muller-Gritschneder, Ulf Schlichtmann Simulation and Modeling 2011-IC-21
Nebel, Wolfgang
2011
Challenges of Multi- and Many-Core Architectures for Electronic System-Level Design Kim Gruttner, Philipp A. Hartmann, Wolfgang Nebel     SPECIAL SESSION 2: What's next for ESL 2011-IC-46
Nelson, Andrew
2011
Composable Power Management with Energy and Power Budgets per Application Andrew Nelson, Anca M. Molnos, Kees Goossens     SPECIAL SESSION 3: Adaptive Systems 2011-IC-55
Neukirchner, Moritz
2011
Admission Control and Self-Configuration in the EPOC Framework Steffen Stein, Moritz Neukirchner, Rolf Ernst SPECIAL SESSION 3: Adaptive Systems 2011-IC-51
Nikolopoulos, Dimitrios S.
2011
Task-based Parallel H.264 Video Encoding for Explicit Communication Architectures Michail Alvanos, George Tzenakis, Dimitrios S. Nikolopoulos, Angelos Bilas  Image and Video Processing 2011-IC-29
Nugteren, Cedric
2011
Skeleton-based Automatic Parallelization of Image Processing Algorithms for GPUs Cedric Nugteren, Henk Corporaal, Bart Mesman Multicore Programming 2011-IC-06
Nylanden, Teemu
2011
FPGA Based Application Specific Processing for Sensor Nodes Teemu Nylanden, Janne Janhunen, Jari Hannuksela, Olli Silven  Accelerators 2011-IC-17
Oey, Oliver
2011
Heterogeneous and Runtime Parameterizable Star-Wheels Network-on-Chip Diana Goehringer, Oliver Oey, Michael Hubner, Jürgen Becker    SPECIAL SESSION 3: Adaptive Systems 2011-IC-53
Oh, Hyunok
2011
Software Synthesis in the ESL Methodology for Multicore Embedded Systems Soonhoi Ha, Hyunok Oh     SPECIAL SESSION 2: What's next for ESL 2011-IC-49
Pegatoquet, Alain
2011
A Performance Estimation Flow for Embedded Systems with Mixed Software/Hardware Modeling Joffrey Kriegel, Alain Pegatoquet, Michel Auguin, Florian Broekaert  Simulation and Modeling 2011-IC-24
Penry, David A.
2011
ADL-Based Specification of Implementation Styles for Functional Simulators David A. Penry, Kurtis D. Cahill Simulation and Modeling 2011-IC-23
Pimentel, Andy D.
2011
Design Metrics and Visualization Techniques for Analyzing the Performance of MOEAs in DSE Toktam Taghavi, Andy D. Pimentel Design Space Exploration 2011-IC-11
Pirsch, Peter
2011
Using SDRAMs for two-dimensional accesses of long 2n × 2m-point FFTs and transposing Stefan Langemeyer, Peter Pirsch, Holger Blume Memory and Communication Strategies 2011-IC-32
Pitkänen, Teemu
2011
Instruction Buffer with Limited Control Flow and Loop Nest Support Vladimír Guzma, Teemu Pitkänen, Jarmo Takala Memory and Communication Strategies 2011-IC-35
Poon, Chi-Sang
2011
On-Chip Dynamic Programming Networks Using 3D-TSV Integration Ra’ed Al-Dujaily, Terrence Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alex Yakovlev, Chi-Sang Poon SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-43
Ramirez, Alex
2011
Supercomputing: Past, Present, and a possible future Alex Ramirez  SAMOS XI - Keynote 2011-IC-02
Ramirez, Alex
2011
Breaking the Bandwidth Wall in Chip Multiprocessors Augusto Vega, Felipe Cabarcas, Alex Ramirez, Mateo Valero  Memory and Communication Strategies 2011-IC-34
Rana, Vincenzo
2011
On-Chip Network Resource Management Design and Validation Francesco Bruschi, Antonio Miele, Vincenzo Rana Memory and Communication Strategies 2011-IC-33
Ravindran, Binoy
2011
On STM Concurrency Control for Multicore Embedded Real-Time Software Sherif Fahmy, Binoy Ravindran Multicore Programming 2011-IC-03
Roma, Nuno
2011
High Throughput and Scalable Architecture for Unified Transform Coding in Embedded H.264/AVC Video Coding Systems Tiago Dias, Sebastian Lopez, Nuno Roma, Leonel Sousa  Image and Video Processing 2011-IC-30
Rotem, Nadav
2011
Optimizing Wait-States in the Synthesis of Memory References with Unpredictable Latencies Yosi Ben Asher, Ron Meldiner, Nadav Rotem Memory and Communication Strategies 2011-IC-36
Rovers, Kenneth C.
2011
Multi-domain transformational design flow for embedded systems Kenneth C. Rovers, Marcel D. van de Burgwal, Jan Kuper, Andre B.J. Kokkeler, Gerard J. M. Smit  Design Space Exploration 2011-IC-14
Salminen, Erno
2011
TCEMC: A Co-Design Flow for Application-Specific Multicores Pekka Jääskeläinen, Erno Salminen, Carlos S. de la Lama, Jarmo Takala, Jose Ignacio Martinez  Design Space Exploration 2011-IC-13
Salminen, Erno
2011
Multicore Communications API (MCAPI) implementation on an FPGA multiprocessor Lauri Matilainen, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen  Memory and Communication Strategies 2011-IC-38
Schewior, Gregor
2011
A Hardware Accelerated Configurable ASIP Architecture for Embedded Real-Time Video-Based Driver Assistance Applications Gregor Schewior, Holger Flatt, Carsten Dolar, Christian Banz, Holger Blume  Image and Video Processing 2011-IC-28
Schlichtmann, Ulf
2011
Removal of Unnecessary Context Switches from the SystemC Simulation Kernel for Fast VP Simulation Kun Lu, Daniel Muller-Gritschneder, Ulf Schlichtmann Simulation and Modeling 2011-IC-21
Schulte, Michael
2011
Analyzing the Performance and Energy Impact of 3D Memory Integration on Embedded DSPs Daniel W. Chang, Nam S. Kim, Michael Schulte  SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-41
Sciuto, Donatella
2011
Dedicated Hardware Accelerators for the Epistatic Analysis of Human Genetic Data Fabio Cancare, Alessandro Marin, Donatella Sciuto Accelerators 2011-IC-15
Seeker, Volker
2011
Scalable Multi-Core Simulation Using Parallel Dynamic Binary Translation Oscar Almer, Igor Bohm, Tobias Edler von Koch, Bjorn Franke, Stephen Kyle, Volker Seeker   Simulation and Modeling 2011-IC-26
Shabbir, Ahsan
2011
Distributed Resource Management for Concurrent Execution of Multimedia Applications on MPSoC Platforms Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal  Accelerators 2011-IC-19
She, Dongrui
2011
MOVE-Pro: a Low Power and High Code Density TTA Architecture Yifan He, Dongrui She, Bart Mesman, Henk Corporaal  Memory and Communication Strategies 2011-IC-39
Sheng, Weihua
2011
Trends in Embedded Software Synthesis Jeronimo Castrillon, Weihua Sheng, Rainer Leupers SPECIAL SESSION 2: What's next for ESL 2011-IC-48
Siauw, Winston
2011
Functional Unit Sharing Between Stacked Processors in 3D Integrated Systems Demid Borodin, Winston Siauw, Sorin Dan Cotofana  SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-42
Silven, Olli
2011
FPGA Based Application Specific Processing for Sensor Nodes Teemu Nylanden, Janne Janhunen, Jari Hannuksela, Olli Silven  Accelerators 2011-IC-17
Siozios, Kostas
2011
Thermal optimization for micro-architectures through selective block replication Dionisios Diamantopoulos, Kostas Siozios, Sotirios Xydis, Dimitrios Soudris  Energy-Aware and Low-Power Designs 2011-IC-10
Smit, Gerard J. M.
2011
Multi-domain transformational design flow for embedded systems Kenneth C. Rovers, Marcel D. van de Burgwal, Jan Kuper, Andre B.J. Kokkeler, Gerard J. M. Smit  Design Space Exploration 2011-IC-14
Smit, Gerard J. M.
2011
Introduction to the Special Session on "Adaptive Systems" Gerard J. M. Smit     SPECIAL SESSION 3: Adaptive Systems 2011-IC-50
Smit, Gerard J. M.
2011
Adaptive resource allocation for streaming applications Timon D. ter Braak, Hermen A. Toersche, Andre B.J. Kokkeler, Gerard J. M. Smit    SPECIAL SESSION 3: Adaptive Systems 2011-IC-54
Somers, Lou
2011
Integrated Model-Driven Design-Space Exploration for Embedded Systems  Nikola Trcka, Martijn Hendriks, Twan Basten, Marc Geilen, Lou Somers    SPECIAL SESSION 2: What's next for ESL 2011-IC-47
Soudris, Dimitrios
2011
Thermal optimization for micro-architectures through selective block replication Dionisios Diamantopoulos, Kostas Siozios, Sotirios Xydis, Dimitrios Soudris  Energy-Aware and Low-Power Designs 2011-IC-10
Sousa, Leonel
2011
High Throughput and Scalable Architecture for Unified Transform Coding in Embedded H.264/AVC Video Coding Systems Tiago Dias, Sebastian Lopez, Nuno Roma, Leonel Sousa  Image and Video Processing 2011-IC-30
Spinean, Bogdan
2011
Vector Processor Customization for FFT Bogdan Spinean, Georgi Kuzmanov, Georgi N. Gaydadjiev Accelerators 2011-IC-16
Stein, Steffen
2011
Admission Control and Self-Configuration in the EPOC Framework Steffen Stein, Moritz Neukirchner, Rolf Ernst SPECIAL SESSION 3: Adaptive Systems 2011-IC-51
Streubuhr, Martin
2011
Calibration and Validation of Software Performance Models for Pedestrian Detection Systems Rainer Kiesel, Martin Streubuhr, Christian Haubelt, Otto Lohlein, Jürgen Teich  Simulation and Modeling 2011-IC-25
Stripf, Timo
2011
Architecture Design Space Exploration of Run-Time Scalable Issue-Width Processors Ralf Koenig, Timo Stripf, Jan Heisswolf, Jürgen Becker  Design Space Exploration 2011-IC-12
Stripf, Timo
2011
A Novel ADL-based Compiler-Centric Software Framework for Reconfigurable Mixed-ISA Processors Timo Stripf, Ralf Koenig, Jürgen Becker Simulation and Modeling 2011-IC-22
Stuijk, Sander
2011
Scenario-Aware Dataflow: Modeling, Analysis and Implementation of Dynamic Applications Sander Stuijk, Marc Geilen, Bart Theelen, Twan Basten    SPECIAL SESSION 3: Adaptive Systems 2011-IC-56
Sundararajan, Karthik T.
2011
Smart Cache: A Self Adaptive Cache Architecture for Energy Efficiency Karthik T. Sundararajan, Timothy M. Jones, Nigel Topham Energy-Aware and Low-Power Designs 2011-IC-08
Taghavi, Toktam
2011
Design Metrics and Visualization Techniques for Analyzing the Performance of MOEAs in DSE Toktam Taghavi, Andy D. Pimentel Design Space Exploration 2011-IC-11
Takala, Jarmo
2011
TCEMC: A Co-Design Flow for Application-Specific Multicores Pekka Jääskeläinen, Erno Salminen, Carlos S. de la Lama, Jarmo Takala, Jose Ignacio Martinez  Design Space Exploration 2011-IC-13
Takala, Jarmo
2011
Instruction Buffer with Limited Control Flow and Loop Nest Support Vladimír Guzma, Teemu Pitkänen, Jarmo Takala Memory and Communication Strategies 2011-IC-35
Teich, Jürgen
2011
Calibration and Validation of Software Performance Models for Pedestrian Detection Systems Rainer Kiesel, Martin Streubuhr, Christian Haubelt, Otto Lohlein, Jürgen Teich  Simulation and Modeling 2011-IC-25
ter Braak, Timon D.
2011
Adaptive resource allocation for streaming applications Timon D. ter Braak, Hermen A. Toersche, Andre B.J. Kokkeler, Gerard J. M. Smit    SPECIAL SESSION 3: Adaptive Systems 2011-IC-54
Theelen, Bart
2011
Scenario-Aware Dataflow: Modeling, Analysis and Implementation of Dynamic Applications Sander Stuijk, Marc Geilen, Bart Theelen, Twan Basten    SPECIAL SESSION 3: Adaptive Systems 2011-IC-56
Thorolfsson, Thor
2011
3D Specific Systems Design and CAD Paul D. Franzon, Thor Thorolfsson, W. Rhett Davis, Samson Melamed SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-44
Toersche, Hermen A.
2011
Adaptive resource allocation for streaming applications Timon D. ter Braak, Hermen A. Toersche, Andre B.J. Kokkeler, Gerard J. M. Smit    SPECIAL SESSION 3: Adaptive Systems 2011-IC-54
Topham, Nigel
2011
Smart Cache: A Self Adaptive Cache Architecture for Energy Efficiency Karthik T. Sundararajan, Timothy M. Jones, Nigel Topham Energy-Aware and Low-Power Designs 2011-IC-08
Trcka, Nikola
2011
Integrated Model-Driven Design-Space Exploration for Embedded Systems  Nikola Trcka, Martijn Hendriks, Twan Basten, Marc Geilen, Lou Somers    SPECIAL SESSION 2: What's next for ESL 2011-IC-47
Tzenakis, George
2011
Task-based Parallel H.264 Video Encoding for Explicit Communication Architectures Michail Alvanos, George Tzenakis, Dimitrios S. Nikolopoulos, Angelos Bilas  Image and Video Processing 2011-IC-29
Valero, Mateo
2011
Breaking the Bandwidth Wall in Chip Multiprocessors Augusto Vega, Felipe Cabarcas, Alex Ramirez, Mateo Valero  Memory and Communication Strategies 2011-IC-34
van de Burgwal, Marcel D.
2011
Multi-domain transformational design flow for embedded systems Kenneth C. Rovers, Marcel D. van de Burgwal, Jan Kuper, Andre B.J. Kokkeler, Gerard J. M. Smit  Design Space Exploration 2011-IC-14
Vega, Augusto
2011
Breaking the Bandwidth Wall in Chip Multiprocessors Augusto Vega, Felipe Cabarcas, Alex Ramirez, Mateo Valero  Memory and Communication Strategies 2011-IC-34
von Koch, Tobias Edler
2011
Scalable Multi-Core Simulation Using Parallel Dynamic Binary Translation Oscar Almer, Igor Bohm, Tobias Edler von Koch, Bjorn Franke, Stephen Kyle, Volker Seeker   Simulation and Modeling 2011-IC-26
Wallentowitz, Stefan
2011
Accelerating Collective Communication in Message Passing on Manycore System-on-Chip Stefan Wallentowitz, Marcel Meyer, Thomas Wild, Andreas Herkersdorf  Multicore Programming 2011-IC-04
Wild, Thomas
2011
Accelerating Collective Communication in Message Passing on Manycore System-on-Chip Stefan Wallentowitz, Marcel Meyer, Thomas Wild, Andreas Herkersdorf  Multicore Programming 2011-IC-04
Wu, Yun
2011
A Kernel Interleaved Scheduling Method for Streaming Applications on Soft-core Vector Processors Chengwei Zheng, John McAllister, Yun Wu Memory and Communication Strategies 2011-IC-37
Xydis, Sotirios
2011
Thermal optimization for micro-architectures through selective block replication Dionisios Diamantopoulos, Kostas Siozios, Sotirios Xydis, Dimitrios Soudris  Energy-Aware and Low-Power Designs 2011-IC-10
Yakovlev, Alex
2011
Power Adaptive Computing System Design in Energy Harvesting Environment Qiang Liu, Terrence Mak, Junwen Luo, Wayne Luk, Alex Yakovlev  Energy-Aware and Low-Power Designs 2011-IC-07
Yakovlev, Alex
2011
On-Chip Dynamic Programming Networks Using 3D-TSV Integration Ra’ed Al-Dujaily, Terrence Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alex Yakovlev, Chi-Sang Poon SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-43
Zhang, Tong
2011
Introduction to the Special Session on "3D Chips: Challenges and Opportunities" Tong Zhang SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-40
Zheng, Chengwei
2011
A Kernel Interleaved Scheduling Method for Streaming Applications on Soft-core Vector Processors Chengwei Zheng, John McAllister, Yun Wu Memory and Communication Strategies 2011-IC-37
Zhou, Kuan
2011
On-Chip Dynamic Programming Networks Using 3D-TSV Integration Ra’ed Al-Dujaily, Terrence Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alex Yakovlev, Chi-Sang Poon SPECIAL SESSION 1: 3D Chips: Challenges and Opportunities 2011-IC-43
Aboulhamid, El Mostapha
2012
System Modeling and Multicore Simulation Using Transactions Amine Anane, El Mostapha Aboulhamid, Yvon Savaria Embedded Simulation 2012-IC-06
Alefragis, Panayiotis
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Alfaro, Francisco J.
2012
OSR-Lite: Fast and Deadlock-Free NoC Reconfiguration Framework Alessandro Strano, Davide Bertozzi, Francisco Trivino, Jose L. Sanchez, Francisco J. Alfaro, Jose Flich Memory & Comms. Strategies 2012-IC-11
Almeida, Gabriel Marchesan
2012
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jürgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire   Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-29
Anane, Amine
2012
System Modeling and Multicore Simulation Using Transactions Amine Anane, El Mostapha Aboulhamid, Yvon Savaria Embedded Simulation 2012-IC-06
Andersch, Michael
2012
Using OpenMP Superscalar for Parallelization of Embedded and Consumer Applications Michael Andersch, Chi Ching Chi, Ben Juurlink Design Space Exploration 2012-IC-04
Anjam, Fakhar
2012
Simultaneous Reconfiguration of Issue-width and Instruction Cache for a VLIW Processor Fakhar Anjam, Stephan Wong, Luigi Carro, Gabriel L. Nazar, Mateus B. Rutzig Embedded Processor Design 2012-IC-23
Annaswamy, Anuradha
2012
Challenges in Automotive Cyber-physical Systems Design Dip Goswami, Reinhard Schneider, Alejandro Masrur, Martin Lukasiewycz, Samarjit Chakraborty, Harald Voit, Anuradha Annaswamy Special Session on Aspects Of Cyber-Physical Systems 2012-IC-49
Aridhi, Slaheddine
2012
Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph Karol Desnos, Maxime Pelcat, Jean-Francois Nezan, Slaheddine Aridhi Dataflow Analysis 2012-IC-20
Arora, Manish
2012
Efficient System Design using the Statistical Analysis of Architectural Bottlenecks Methodology Manish Arora, Feng Wang, Bob Rychlik, Dean M. Tullsen ESL Tools & Methods 2012-IC-27
Ascheid, Gerd
2012
Just-in-Time Verification in ADL-based Processor Design Dominik Auras, Andreas Minwegen, Uwe Deidersen, Stefan Scurmans, Gerd Ascheid, Rainer Leupers Design Space Exploration 2012-IC-01
Ascheid, Gerd
2012
Throughput Driven Transformations of Synchronous Data Flows for Mapping to Heterogeneous MPSoCs Anastasia Stulova, Rainer Leupers, Gerd Ascheid Dataflow Application Synthesis 2012-IC-18
Ascheid, Gerd
2012
An FPGA-Accelerated Testbed for Hardware Component Development in MIMO Wireless Communication Systems Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-37
Athanasiou, George S.
2012
A Template-based Methodology for Efficient Microprocessor and FPGA Accelerator Co-Design Angeliki Kritikakou, Francky Catthoor, George S. Athanasiou, Vasilios Kelefouras, Costas Goutis  Design Space Exploration 2012-IC-03
Auras, Dominik
2012
Just-in-Time Verification in ADL-based Processor Design Dominik Auras, Andreas Minwegen, Uwe Deidersen, Stefan Scurmans, Gerd Ascheid, Rainer Leupers Design Space Exploration 2012-IC-01
Auras, Dominik
2012
An FPGA-Accelerated Testbed for Hardware Component Development in MIMO Wireless Communication Systems Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-37
Bartzas, Alexandros
2012
Adaptive dynamic memory allocators by estimating application workloads Ioannis Koutras, Alexandros Bartzas, Dimitrios Soudris Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-32
Basten, Twan
2012
Predictable Dynamic Embedded Data Processing Marc Geilen, Sander Stuijk, Twan Basten Special Session on Aspects Of Cyber-Physical Systems 2012-IC-44
Baudisch, Daniel
2012
Out-Of-Order Execution of Synchronous Data-Flow Networks Daniel Baudisch, Jens Brandt, Klaus Schneider Dataflow Analysis 2012-IC-21
Bayrak, Ali Galip
2012
Counting Stream Registers: An Efficient and Effective Snoop Filter Architecture Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne Domain-Specific Architectures 2012-IC-15
Becker, Jürgen
2012
Adaptive Processor Architecture Michael Hubner, Diana Goehringer, Carsten Tradowky, Joerg Henkel, Jürgen Becker Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-31
Becker, Jürgen
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Becker, Jürgen
2012
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jürgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire   Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-29
Bekooij, Marco J.G.
2012
An Efficient Asymmetric Distributed Lock for Embedded Multiprocessor Systems Jochem H. Rutgers, Marco J.G. Bekooij, Gerard J. M. Smit Embedded Processor Design 2012-IC-22
Ben-Itzhak, Yaniv
2012
HNOCS: Modular Open-Source Simulator for Heterogeneous NoCs Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny Embedded Simulation 2012-IC-07
Benini, Luca
2012
A Tightly-Coupled Multi-Core Cluster with Shared-Memory HW Accelerators Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Naser Yazdani Memory & Comms. Strategies 2012-IC-12
Bertozzi, Davide
2012
OSR-Lite: Fast and Deadlock-Free NoC Reconfiguration Framework Alessandro Strano, Davide Bertozzi, Francisco Trivino, Jose L. Sanchez, Francisco J. Alfaro, Jose Flich Memory & Comms. Strategies 2012-IC-11
Bhattacharyya, Shuvra S.
2012
Instrumentation Techniques for Cyber-Physical Systems Using the Targeted Dataflow Interchange Format Shuvra S. Bhattacharyya Special Session on Aspects Of Cyber-Physical Systems 2012-IC-51
Blume, Holger
2012
Introduction to the Special Session on FPGA-based Emulation of Hardware Architectures  Holger Blume Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-35
Bodin, Bruno
2012
K-Periodic Schedules for Evaluating the Maximum Throughput of a Synchronous Dataflow Graph Bruno Bodin, Alix Munier-Kordon, Benoit Dupont de Dinechin Dataflow Analysis 2012-IC-19
Bonetto, Alessandra
2012
TaBit: a Framework for Task Graph to Bitstream Generation Alessandra Bonetto, Andrea Cazzaniga, Gianluca C. Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio ESL Tools & Methods 2012-IC-25
Borlenghi, Filippo
2012
An FPGA-Accelerated Testbed for Hardware Component Development in MIMO Wireless Communication Systems Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-37
Boutellier, Jani
2012
Reconfigurable Miniature Sensor Nodes for Condition Monitoring Teemu Nylanden, Jani Boutellier, Karri Nikunen, Jari Hannuksela, Olli Silven Domain-Specific Architectures 2012-IC-14
Brandstatter, Siegfried
2012
An Application-Specific Network-on-Chip for Control Architectures in RF Transceivers Siegfried Brandstatter, Mario Huemer Memory & Comms. Strategies 2012-IC-09
Brandt, Jens
2012
Out-Of-Order Execution of Synchronous Data-Flow Networks Daniel Baudisch, Jens Brandt, Klaus Schneider Dataflow Analysis 2012-IC-21
Brisk, Philip
2012
Counting Stream Registers: An Efficient and Effective Snoop Filter Architecture Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne Domain-Specific Architectures 2012-IC-15
Broenink, Jan F.
2012
Model-Driven Robot-Software Design using integrated Models and Co-Simulation Jan F. Broenink, Yunyun Ni Special Session on Aspects Of Cyber-Physical Systems 2012-IC-47
Cardoso, João M. P.
2012
Hardware/Software Specialization Through Aspects: The LARA Approach João M. P. Cardoso, Tiago Carvalho, Joao Teixeira, Pedro C. Diniz, Fernando Goncalves, Zlatko Petrov Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-33
Carro, Luigi
2012
Simultaneous Reconfiguration of Issue-width and Instruction Cache for a VLIW Processor Fakhar Anjam, Stephan Wong, Luigi Carro, Gabriel L. Nazar, Mateus B. Rutzig Embedded Processor Design 2012-IC-23
Carvalho, Tiago
2012
Hardware/Software Specialization Through Aspects: The LARA Approach João M. P. Cardoso, Tiago Carvalho, Joao Teixeira, Pedro C. Diniz, Fernando Goncalves, Zlatko Petrov Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-33
Catthoor, Francky
2012
A Template-based Methodology for Efficient Microprocessor and FPGA Accelerator Co-Design Angeliki Kritikakou, Francky Catthoor, George S. Athanasiou, Vasilios Kelefouras, Costas Goutis  Design Space Exploration 2012-IC-03
Cazzaniga, Andrea
2012
TaBit: a Framework for Task Graph to Bitstream Generation Alessandra Bonetto, Andrea Cazzaniga, Gianluca C. Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio ESL Tools & Methods 2012-IC-25
Chakraborty, Samarjit
2012
Challenges in Automotive Cyber-physical Systems Design Dip Goswami, Reinhard Schneider, Alejandro Masrur, Martin Lukasiewycz, Samarjit Chakraborty, Harald Voit, Anuradha Annaswamy Special Session on Aspects Of Cyber-Physical Systems 2012-IC-49
Chana, Anne-Marie
2012
Efficient Hardware Implementation of Data-Flow Parallel Embedded Systems Patrice Quinton, Anne-Marie Chana, Steven Derrien Special Session on Aspects Of Cyber-Physical Systems 2012-IC-52
Chang, Chen
2012
BEE technology overview Joseph Rothman, Chen Chang Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-36
Charbon, Edoardo
2012
Counting Stream Registers: An Efficient and Effective Snoop Filter Architecture Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne Domain-Specific Architectures 2012-IC-15
Chi, Chi Ching
2012
Using OpenMP Superscalar for Parallelization of Embedded and Consumer Applications Michael Andersch, Chi Ching Chi, Ben Juurlink Design Space Exploration 2012-IC-04
Cidon, Israel
2012
HNOCS: Modular Open-Source Simulator for Heterogeneous NoCs Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny Embedded Simulation 2012-IC-07
Corvino, Rosilde
2012
Design Space Exploration in Application-Specific Hardware Synthesis for Multiple Communicating Nested Loops Rosilde Corvino, Abdoulaye Gamatie, Marc Geilen, Lech Jozwiak Dataflow Application Synthesis 2012-IC-16
Daneshtalab, Masoud
2012
Adaptive Reinforcement Learning Method for Networks-on-Chip Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Pasi Liljeberg Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-30
Datsios, Chrysovalantis
2012
A Framework for Efficient Cache Resizing Georgios Keramidas, Chrysovalantis Datsios, Stefanos Kaxiras Memory & Comms. Strategies 2012-IC-10
de Dinechin, Benoit Dupont
2012
K-Periodic Schedules for Evaluating the Maximum Throughput of a Synchronous Dataflow Graph Bruno Bodin, Alix Munier-Kordon, Benoit Dupont de Dinechin Dataflow Analysis 2012-IC-19
Dehyadegari, Masoud
2012
A Tightly-Coupled Multi-Core Cluster with Shared-Memory HW Accelerators Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Naser Yazdani Memory & Comms. Strategies 2012-IC-12
Deidersen, Uwe
2012
Just-in-Time Verification in ADL-based Processor Design Dominik Auras, Andreas Minwegen, Uwe Deidersen, Stefan Scurmans, Gerd Ascheid, Rainer Leupers Design Space Exploration 2012-IC-01
Deprettere, Ed F.
2012
Introduction to the Special Session on  Aspects Of Cyber-Physical Systems  Ed Deprettere Special Session on Aspects Of Cyber-Physical Systems 2012-IC-42
Derrien, Steven
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Derrien, Steven
2012
Efficient Hardware Implementation of Data-Flow Parallel Embedded Systems Patrice Quinton, Anne-Marie Chana, Steven Derrien Special Session on Aspects Of Cyber-Physical Systems 2012-IC-52
Desnos, Karol
2012
Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph Karol Desnos, Maxime Pelcat, Jean-Francois Nezan, Slaheddine Aridhi Dataflow Analysis 2012-IC-20
Dimitroulakos, Grigoris
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Diniz, Pedro C.
2012
Introduction to the Special Session on Programming Paradigms for Reconfigurable Multi-Core Embedded Systems  Diana Goehringer, Pedro Diniz Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-28
Diniz, Pedro C.
2012
Hardware/Software Specialization Through Aspects: The LARA Approach João M. P. Cardoso, Tiago Carvalho, Joao Teixeira, Pedro C. Diniz, Fernando Goncalves, Zlatko Petrov Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-33
Durelli, Gianluca C.
2012
TaBit: a Framework for Task Graph to Bitstream Generation Alessandra Bonetto, Andrea Cazzaniga, Gianluca C. Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio ESL Tools & Methods 2012-IC-25
Ebrahimi, Masoumeh
2012
Adaptive Reinforcement Learning Method for Networks-on-Chip Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Pasi Liljeberg Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-30
Engel, Michael
2012
Efficient Computing in Cyber-Physical Systems Peter Marwedel, Michael Engel Special Session on Aspects Of Cyber-Physical Systems 2012-IC-45
Farahnakian, Fahimeh
2012
Adaptive Reinforcement Learning Method for Networks-on-Chip Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Pasi Liljeberg Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-30
Flich, Jose
2012
OSR-Lite: Fast and Deadlock-Free NoC Reconfiguration Framework Alessandro Strano, Davide Bertozzi, Francisco Trivino, Jose L. Sanchez, Francisco J. Alfaro, Jose Flich Memory & Comms. Strategies 2012-IC-11
Gamatie, Abdoulaye
2012
Design Space Exploration in Application-Specific Hardware Synthesis for Multiple Communicating Nested Loops Rosilde Corvino, Abdoulaye Gamatie, Marc Geilen, Lech Jozwiak Dataflow Application Synthesis 2012-IC-16
Gaydadjiev, Georgi N.
2012
Architecture-Level Fault-Tolerance for Biomedical Implants Robert M. Seepers, Christos Strydis, Georgi N. Gaydadjiev Domain-Specific Architectures 2012-IC-13
Geilen, Marc
2012
Design Space Exploration in Application-Specific Hardware Synthesis for Multiple Communicating Nested Loops Rosilde Corvino, Abdoulaye Gamatie, Marc Geilen, Lech Jozwiak Dataflow Application Synthesis 2012-IC-16
Geilen, Marc
2012
Predictable Dynamic Embedded Data Processing Marc Geilen, Sander Stuijk, Twan Basten Special Session on Aspects Of Cyber-Physical Systems 2012-IC-44
Glass, Michael
2012
A Co-simulation Approach for System-Level Analysis of Embedded Control Systems Michael Glass, Jürgen Teich, Liyuan Zhang Special Session on Aspects Of Cyber-Physical Systems 2012-IC-50
Goehringer, Diana
2012
Introduction to the Special Session on Programming Paradigms for Reconfigurable Multi-Core Embedded Systems  Diana Goehringer, Pedro Diniz Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-28
Goehringer, Diana
2012
Adaptive Processor Architecture Michael Hubner, Diana Goehringer, Carsten Tradowky, Joerg Henkel, Jüurgen Becker Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-31
Goehringer, Diana
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Gogos, Christos
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Goncalves, Fernando
2012
Hardware/Software Specialization Through Aspects: The LARA Approach João M. P. Cardoso, Tiago Carvalho, Joao Teixeira, Pedro C. Diniz, Fernando Goncalves, Zlatko Petrov Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-33
Goossens, Kees
2012
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jürgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire   Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-29
Goswami, Dip
2012
Challenges in Automotive Cyber-physical Systems Design Dip Goswami, Reinhard Schneider, Alejandro Masrur, Martin Lukasiewycz, Samarjit Chakraborty, Harald Voit, Anuradha Annaswamy Special Session on Aspects Of Cyber-Physical Systems 2012-IC-49
Goulas, George
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Goutis, Costas
2012
A Template-based Methodology for Efficient Microprocessor and FPGA Accelerator Co-Design Angeliki Kritikakou, Francky Catthoor, George S. Athanasiou, Vasilios Kelefouras, Costas Goutis  Design Space Exploration 2012-IC-03
Hamalainen, Timo D.
2012
System-on-Chip deployment with MCAPI abstraction and IP-XACT metadata Lauri Matilainen, Lasse Lehtonen, Joni-Matti Maatta, Erno Salminen, Timo D. Hamalainen ESL Tools & Methods 2012-IC-26
Hannuksela, Jari
2012
Reconfigurable Miniature Sensor Nodes for Condition Monitoring Teemu Nylanden, Jani Boutellier, Karri Nikunen, Jari Hannuksela, Olli Silven Domain-Specific Architectures 2012-IC-14
Haubelt, Christian
2012
Virtual Prototyping for Efficient Multi-Core ECU Development of Driver Assistance Systems Rainer Kiesel, Martin Streubuhr, Christian Haubelt, Anestis Terzis, Jürgen Teich Embedded Simulation 2012-IC-05
Henkel, Joerg
2012
Adaptive Processor Architecture Michael Hubner, Diana Goehringer, Carsten Tradowky, Joerg Henkel, Jürgen Becker Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-31
Herkersdorf, Andreas
2012
Multicore Enablement for Cyber Physical Systems Andreas Herkersdorf Special Session on Aspects Of Cyber-Physical Systems 2012-IC-48
Hubner, Michael
2012
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jürgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire   Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-29
Hubner, Michael
2012
Adaptive Processor Architecture Michael Hubner, Diana Goehringer, Carsten Tradowky, Joerg Henkel, Jürgen Becker Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-31
Hubner, Michael
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Huemer, Mario
2012
An Application-Specific Network-on-Chip for Control Architectures in RF Transceivers Siegfried Brandstatter, Mario Huemer Memory & Comms. Strategies 2012-IC-09
Ienne, Paolo
2012
Counting Stream Registers: An Efficient and Effective Snoop Filter Architecture Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne Domain-Specific Architectures 2012-IC-15
Jozwiak, Lech
2012
Design Space Exploration in Application-Specific Hardware Synthesis for Multiple Communicating Nested Loops Rosilde Corvino, Abdoulaye Gamatie, Marc Geilen, Lech Jozwiak Dataflow Application Synthesis 2012-IC-16
Juurlink, Ben
2012
Using OpenMP Superscalar for Parallelization of Embedded and Consumer Applications Michael Andersch, Chi Ching Chi, Ben Juurlink Design Space Exploration 2012-IC-04
Kakoee, Mohammad Reza
2012
A Tightly-Coupled Multi-Core Cluster with Shared-Memory HW Accelerators Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Naser Yazdani Memory & Comms. Strategies 2012-IC-12
Kanistras, Nikolaos
2012
An FPGA-based Prototyping Method for Verification, Characterization and Optimization of LDPC Error Correction Systems Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikolaos Kanistras, Ahmed Mahdi, Vassilis Paliouras Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-38
Kavvadias, Nikolaos
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Kaxiras, Stefanos
2012
A Framework for Efficient Cache Resizing Georgios Keramidas, Chrysovalantis Datsios, Stefanos Kaxiras Memory & Comms. Strategies 2012-IC-10
Kelefouras, Vasilios
2012
A Template-based Methodology for Efficient Microprocessor and FPGA Accelerator Co-Design Angeliki Kritikakou, Francky Catthoor, George S. Athanasiou, Vasilios Kelefouras, Costas Goutis  Design Space Exploration 2012-IC-03
Kempf, Torsten
2012
An FPGA-Accelerated Testbed for Hardware Component Development in MIMO Wireless Communication Systems Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-37
Keramidas, Georgios
2012
A Framework for Efficient Cache Resizing Georgios Keramidas, Chrysovalantis Datsios, Stefanos Kaxiras Memory & Comms. Strategies 2012-IC-10
Kiesel, Rainer
2012
Virtual Prototyping for Efficient Multi-Core ECU Development of Driver Assistance Systems Rainer Kiesel, Martin Streubuhr, Christian Haubelt, Anestis Terzis, Jürgen Teich Embedded Simulation 2012-IC-05
Kluter, Theo
2012
Counting Stream Registers: An Efficient and Effective Snoop Filter Architecture Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne Domain-Specific Architectures 2012-IC-15
Koedam, Martijn
2012
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jürgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire   Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-29
Kolodny, Avinoam
2012
HNOCS: Modular Open-Source Simulator for Heterogeneous NoCs Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny Embedded Simulation 2012-IC-07
Korb, Matthias
2012
A Quantitative Analysis of Fixed-Point LDPC-Decoder Implementations using Hardware-Accelerated HDL Emulations Matthias Korb, Tobias G. Noll Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-39
Koutras, Ioannis
2012
Adaptive dynamic memory allocators by estimating application workloads Ioannis Koutras, Alexandros Bartzas, Dimitrios Soudris Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-32
Kritharidis, Dimitrios
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Kritikakou, Angeliki
2012
A Template-based Methodology for Efficient Microprocessor and FPGA Accelerator Co-Design Angeliki Kritikakou, Francky Catthoor, George S. Athanasiou, Vasilios Kelefouras, Costas Goutis  Design Space Exploration 2012-IC-03
Lehtonen, Lasse
2012
System-on-Chip deployment with MCAPI abstraction and IP-XACT metadata Lauri Matilainen, Lasse Lehtonen, Joni-Matti Maatta, Erno Salminen, Timo D. Hamalainen ESL Tools & Methods 2012-IC-26
Lemaire, Romain
2012
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jürgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire   Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-29
Lemonnier, Fabrice
2012
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jürgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire   Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-29
Leupers, Rainer
2012
Just-in-Time Verification in ADL-based Processor Design Dominik Auras, Andreas Minwegen, Uwe Deidersen, Stefan Scurmans, Gerd Ascheid, Rainer Leupers Design Space Exploration 2012-IC-01
Leupers, Rainer
2012
Throughput Driven Transformations of Synchronous Data Flows for Mapping to Heterogeneous MPSoCs Anastasia Stulova, Rainer Leupers, Gerd Ascheid Dataflow Application Synthesis 2012-IC-18
Leupers, Rainer
2012
An FPGA-Accelerated Testbed for Hardware Component Development in MIMO Wireless Communication Systems Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-37
Liljeberg, Pasi
2012
Adaptive Reinforcement Learning Method for Networks-on-Chip Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Pasi Liljeberg Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-30
Lukasiewycz, Martin
2012
Challenges in Automotive Cyber-physical Systems Design Dip Goswami, Reinhard Schneider, Alejandro Masrur, Martin Lukasiewycz, Samarjit Chakraborty, Harald Voit, Anuradha Annaswamy Special Session on Aspects Of Cyber-Physical Systems 2012-IC-49
Maatta, Joni-Matti
2012
System-on-Chip deployment with MCAPI abstraction and IP-XACT metadata Lauri Matilainen, Lasse Lehtonen, Joni-Matti Maatta, Erno Salminen, Timo D. Hamalainen ESL Tools & Methods 2012-IC-26
Mahdi, Ahmed
2012
An FPGA-based Prototyping Method for Verification, Characterization and Optimization of LDPC Error Correction Systems Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikolaos Kanistras, Ahmed Mahdi, Vassilis Paliouras Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-38
Marongiu, Andrea
2012
A Tightly-Coupled Multi-Core Cluster with Shared-Memory HW Accelerators Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Naser Yazdani Memory & Comms. Strategies 2012-IC-12
Marwedel, Peter
2012
Efficient Computing in Cyber-Physical Systems Peter Marwedel, Michael Engel Special Session on Aspects Of Cyber-Physical Systems 2012-IC-45
Masrur, Alejandro
2012
Challenges in Automotive Cyber-physical Systems Design Dip Goswami, Reinhard Schneider, Alejandro Masrur, Martin Lukasiewycz, Samarjit Chakraborty, Harald Voit, Anuradha Annaswamy Special Session on Aspects Of Cyber-Physical Systems 2012-IC-49
Masselos, Kostas
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Matilainen, Lauri
2012
System-on-Chip deployment with MCAPI abstraction and IP-XACT metadata Lauri Matilainen, Lasse Lehtonen, Joni-Matti Maatta, Erno Salminen, Timo D. Hamalainen ESL Tools & Methods 2012-IC-26
May, David
2012
An FPGA-based Probability-aware Fault Simulator David May, Walter Stechele Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-40
McAllister, John
2012
Automatic FPGA Synthesis of Memory Intensive C-based Kernels Matthew Milford, John McAllister Dataflow Application Synthesis 2012-IC-17
Meloni, Paolo
2012
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems Paolo Meloni, Sebastiano Pomata, Luigi Raffo, Roberta Piscitelli, Andy D. Pimentel Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-41
Menard, Daniel
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Meyr, Heinrich
2012
An FPGA-Accelerated Testbed for Hardware Component Development in MIMO Wireless Communication Systems Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-37
Michaud, Pierre
2012
BADCO : Behavioral Application-Dependent Superscalar Core Model Ricardo A. Velasquez, Pierre Michaud, Andre Seznec Embedded Simulation 2012-IC-08
Milford, Matthew
2012
Automatic FPGA Synthesis of Memory Intensive C-based Kernels Matthew Milford, John McAllister Dataflow Application Synthesis 2012-IC-17
Millet, Philippe
2012
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jürgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire   Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-29
Minwegen, Andreas
2012
Just-in-Time Verification in ADL-based Processor Design Dominik Auras, Andreas Minwegen, Uwe Deidersen, Stefan Scurmans, Gerd Ascheid, Rainer Leupers Design Space Exploration 2012-IC-01
Mitas, Nikolaos
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Mohammadi, Siamak
2012
A Tightly-Coupled Multi-Core Cluster with Shared-Memory HW Accelerators Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Naser Yazdani Memory & Comms. Strategies 2012-IC-12
Morgan, Marc-Nicolas
2012
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jürgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire   Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-29
Munier-Kordon, Alix
2012
K-Periodic Schedules for Evaluating the Maximum Throughput of a Synchronous Dataflow Graph Bruno Bodin, Alix Munier-Kordon, Benoit Dupont de Dinechin Dataflow Analysis 2012-IC-19
Nazar, Gabriel L.
2012
Simultaneous Reconfiguration of Issue-width and Instruction Cache for a VLIW Processor Fakhar Anjam, Stephan Wong, Luigi Carro, Gabriel L. Nazar, Mateus B. Rutzig Embedded Processor Design 2012-IC-23
Nezan, Jean-Francois
2012
Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph Karol Desnos, Maxime Pelcat, Jean-Francois Nezan, Slaheddine Aridhi Dataflow Analysis 2012-IC-20
Ni, Yunyun
2012
Model-Driven Robot-Software Design using integrated Models and Co-Simulation Jan F. Broenink, Yunyun Ni Special Session on Aspects Of Cyber-Physical Systems 2012-IC-47
Nikunen, Karri
2012
Reconfigurable Miniature Sensor Nodes for Condition Monitoring Teemu Nylanden, Jani Boutellier, Karri Nikunen, Jari Hannuksela, Olli Silven Domain-Specific Architectures 2012-IC-14
Noll, Tobias G.
2012
A Quantitative Analysis of Fixed-Point LDPC-Decoder Implementations using Hardware-Accelerated HDL Emulations Matthias Korb, Tobias G. Noll Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-39
Nylanden, Teemu
2012
Reconfigurable Miniature Sensor Nodes for Condition Monitoring Teemu Nylanden, Jani Boutellier, Karri Nikunen, Jari Hannuksela, Olli Silven Domain-Specific Architectures 2012-IC-14
Oey, Oliver
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Paliouras, Vassilis
2012
An FPGA-based Prototyping Method for Verification, Characterization and Optimization of LDPC Error Correction Systems Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikolaos Kanistras, Ahmed Mahdi, Vassilis Paliouras Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-38
Pelcat, Maxime
2012
Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph Karol Desnos, Maxime Pelcat, Jean-Francois Nezan, Slaheddine Aridhi Dataflow Analysis 2012-IC-20
Petrov, Zlatko
2012
Hardware/Software Specialization Through Aspects: The LARA Approach João M. P. Cardoso, Tiago Carvalho, Joao Teixeira, Pedro C. Diniz, Fernando Goncalves, Zlatko Petrov Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-33
Piguet, Christian
2012
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jürgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire   Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-29
Pilato, Christian
2012
TaBit: a Framework for Task Graph to Bitstream Generation Alessandra Bonetto, Andrea Cazzaniga, Gianluca C. Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio ESL Tools & Methods 2012-IC-25
Pillement, Sebastien
2012
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jürgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire   Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-29
Pimentel, Andy D.
2012
Interleaving Methods for Hybrid System-level MPSoC Design Space Exploration Roberta Piscitelli, Andy D. Pimentel Design Space Exploration 2012-IC-02
Pimentel, Andy D.
2012
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems Paolo Meloni, Sebastiano Pomata, Luigi Raffo, Roberta Piscitelli, Andy D. Pimentel Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-41
Piscitelli, Roberta
2012
Interleaving Methods for Hybrid System-level MPSoC Design Space Exploration Roberta Piscitelli, Andy D. Pimentel Design Space Exploration 2012-IC-02
Piscitelli, Roberta
2012
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems Paolo Meloni, Sebastiano Pomata, Luigi Raffo, Roberta Piscitelli, Andy D. Pimentel Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-41
Plosila, Juha
2012
Adaptive Reinforcement Learning Method for Networks-on-Chip Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Pasi Liljeberg Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-30
Pomata, Sebastiano
2012
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems Paolo Meloni, Sebastiano Pomata, Luigi Raffo, Roberta Piscitelli, Andy D. Pimentel Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-41
Pratas, Frederico
2012
Energy Efficient Stream-based Configurable Architecture for Embedded Platforms Frederico Pratas, Pedro Tomas, Pedro Trancoso, Leonel Sousa Embedded Processor Design 2012-IC-24
Quinton, Patrice
2012
Efficient Hardware Implementation of Data-Flow Parallel Embedded Systems Patrice Quinton, Anne-Marie Chana, Steven Derrien Special Session on Aspects Of Cyber-Physical Systems 2012-IC-52
Raffo, Luigi
2012
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems Paolo Meloni, Sebastiano Pomata, Luigi Raffo, Roberta Piscitelli, Andy D. Pimentel Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-41
Ranganathan, Aanjhan
2012
Counting Stream Registers: An Efficient and Effective Snoop Filter Architecture Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne Domain-Specific Architectures 2012-IC-15
Rauwerda, Gerard
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Rothman, Joseph
2012
BEE technology overview Joseph Rothman, Chen Chang Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-36
Rutgers, Jochem H.
2012
An Efficient Asymmetric Distributed Lock for Embedded Multiprocessor Systems Jochem H. Rutgers, Marco J.G. Bekooij, Gerard J. M. Smit Embedded Processor Design 2012-IC-22
Rutzig, Mateus B.
2012
Simultaneous Reconfiguration of Issue-width and Instruction Cache for a VLIW Processor Fakhar Anjam, Stephan Wong, Luigi Carro, Gabriel L. Nazar, Mateus B. Rutzig Embedded Processor Design 2012-IC-23
Rychlik, Bob
2012
Efficient System Design using the Statistical Analysis of Architectural Bottlenecks Methodology Manish Arora, Feng Wang, Bob Rychlik, Dean M. Tullsen ESL Tools & Methods 2012-IC-27
Sakellariou, Panagiotis
2012
An FPGA-based Prototyping Method for Verification, Characterization and Optimization of LDPC Error Correction Systems Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikolaos Kanistras, Ahmed Mahdi, Vassilis Paliouras Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-38
Salminen, Erno
2012
System-on-Chip deployment with MCAPI abstraction and IP-XACT metadata Lauri Matilainen, Lasse Lehtonen, Joni-Matti Maatta, Erno Salminen, Timo D. Hamalainen ESL Tools & Methods 2012-IC-26
Sanchez, Jose L.
2012
OSR-Lite: Fast and Deadlock-Free NoC Reconfiguration Framework Alessandro Strano, Davide Bertozzi, Francisco Trivino, Jose L. Sanchez, Francisco J. Alfaro, Jose Flich Memory & Comms. Strategies 2012-IC-11
Santambrogio, Marco D.
2012
TaBit: a Framework for Task Graph to Bitstream Generation Alessandra Bonetto, Andrea Cazzaniga, Gianluca C. Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio ESL Tools & Methods 2012-IC-25
Savaria, Yvon
2012
System Modeling and Multicore Simulation Using Transactions Amine Anane, El Mostapha Aboulhamid, Yvon Savaria Embedded Simulation 2012-IC-06
Schneider, Klaus
2012
Out-Of-Order Execution of Synchronous Data-Flow Networks Daniel Baudisch, Jens Brandt, Klaus Schneider Dataflow Analysis 2012-IC-21
Schneider, Reinhard
2012
Challenges in Automotive Cyber-physical Systems Design Dip Goswami, Reinhard Schneider, Alejandro Masrur, Martin Lukasiewycz, Samarjit Chakraborty, Harald Voit, Anuradha Annaswamy Special Session on Aspects Of Cyber-Physical Systems 2012-IC-49
Schoeberl, Martin
2012
Is Time Predictability Quantifiable? Martin Schoeberl Special Session on Aspects Of Cyber-Physical Systems 2012-IC-46
Sciuto, Donatella
2012
TaBit: a Framework for Task Graph to Bitstream Generation Alessandra Bonetto, Andrea Cazzaniga, Gianluca C. Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio ESL Tools & Methods 2012-IC-25
Scurmans, Stefan
2012
Just-in-Time Verification in ADL-based Processor Design Dominik Auras, Andreas Minwegen, Uwe Deidersen, Stefan Scurmans, Gerd Ascheid, Rainer Leupers Design Space Exploration 2012-IC-01
Seepers, Robert M.
2012
Architecture-Level Fault-Tolerance for Biomedical Implants Robert M. Seepers, Christos Strydis, Georgi N. Gaydadjiev Domain-Specific Architectures 2012-IC-13
Sentieys, Olivier
2012
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jürgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire   Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-29
Sentieys, Olivier
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Seznec, Andre
2012
BADCO : Behavioral Application-Dependent Superscalar Core Model Ricardo A. Velasquez, Pierre Michaud, Andre Seznec Embedded Simulation 2012-IC-08
Sifakis, Joseph
2012
Rigorous Design of Cyber-physical Systems Joseph Sifakis Special Session on Aspects Of Cyber-Physical Systems 2012-IC-43
Silven, Olli
2012
Reconfigurable Miniature Sensor Nodes for Condition Monitoring Teemu Nylanden, Jani Boutellier, Karri Nikunen, Jari Hannuksela, Olli Silven Domain-Specific Architectures 2012-IC-14
Sinha, Shubhendu
2012
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jürgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire   Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-29
Smit, Gerard J. M.
2012
An Efficient Asymmetric Distributed Lock for Embedded Multiprocessor Systems Jochem H. Rutgers, Marco J.G. Bekooij, Gerard J. M. Smit Embedded Processor Design 2012-IC-22
Soudris, Dimitrios
2012
Adaptive dynamic memory allocators by estimating application workloads Ioannis Koutras, Alexandros Bartzas, Dimitrios Soudris Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-32
Sousa, Leonel
2012
Energy Efficient Stream-based Configurable Architecture for Embedded Platforms Frederico Pratas, Pedro Tomas, Pedro Trancoso, Leonel Sousa Embedded Processor Design 2012-IC-24
Stechele, Walter
2012
An FPGA-based Probability-aware Fault Simulator David May, Walter Stechele Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-40
Strano, Alessandro
2012
OSR-Lite: Fast and Deadlock-Free NoC Reconfiguration Framework Alessandro Strano, Davide Bertozzi, Francisco Trivino, Jose L. Sanchez, Francisco J. Alfaro, Jose Flich Memory & Comms. Strategies 2012-IC-11
Streubuhr, Martin
2012
Virtual Prototyping for Efficient Multi-Core ECU Development of Driver Assistance Systems Rainer Kiesel, Martin Streubuhr, Christian Haubelt, Anestis Terzis, Jürgen Teich Embedded Simulation 2012-IC-05
Stripf, Timo
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Strydis, Christos
2012
Architecture-Level Fault-Tolerance for Biomedical Implants Robert M. Seepers, Christos Strydis, Georgi N. Gaydadjiev Domain-Specific Architectures 2012-IC-13
Stuijk, Sander
2012
Predictable Dynamic Embedded Data Processing Marc Geilen, Sander Stuijk, Twan Basten Special Session on Aspects Of Cyber-Physical Systems 2012-IC-44
Stulova, Anastasia
2012
Throughput Driven Transformations of Synchronous Data Flows for Mapping to Heterogeneous MPSoCs Anastasia Stulova, Rainer Leupers, Gerd Ascheid Dataflow Application Synthesis 2012-IC-18
Sunesen, Kim
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Teich, Jürgen
2012
Virtual Prototyping for Efficient Multi-Core ECU Development of Driver Assistance Systems Rainer Kiesel, Martin Streubuhr, Christian Haubelt, Anestis Terzis, Jürgen Teich Embedded Simulation 2012-IC-05
Teich, Jürgen
2012
A Co-simulation Approach for System-Level Analysis of Embedded Control Systems Michael Glass, Jürgen Teich, Liyuan Zhang Special Session on Aspects Of Cyber-Physical Systems 2012-IC-50
Teixeira, Joao
2012
Hardware/Software Specialization Through Aspects: The LARA Approach João M. P. Cardoso, Tiago Carvalho, Joao Teixeira, Pedro C. Diniz, Fernando Goncalves, Zlatko Petrov Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-33
Terzis, Anestis
2012
Virtual Prototyping for Efficient Multi-Core ECU Development of Driver Assistance Systems Rainer Kiesel, Martin Streubuhr, Christian Haubelt, Anestis Terzis, Jürgen Teich Embedded Simulation 2012-IC-05
Tomas, Pedro
2012
Energy Efficient Stream-based Configurable Architecture for Embedded Platforms Frederico Pratas, Pedro Tomas, Pedro Trancoso, Leonel Sousa Embedded Processor Design 2012-IC-24
Tradowky, Carsten
2012
Adaptive Processor Architecture Michael Hubner, Diana Goehringer, Carsten Tradowky, Joerg Henkel, Jürgen Becker Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-31
Trancoso, Pedro
2012
Energy Efficient Stream-based Configurable Architecture for Embedded Platforms Frederico Pratas, Pedro Tomas, Pedro Trancoso, Leonel Sousa Embedded Processor Design 2012-IC-24
Trivino, Francisco
2012
OSR-Lite: Fast and Deadlock-Free NoC Reconfiguration Framework Alessandro Strano, Davide Bertozzi, Francisco Trivino, Jose L. Sanchez, Francisco J. Alfaro, Jose Flich Memory & Comms. Strategies 2012-IC-11
Tsatsaragkos, Ioannis
2012
An FPGA-based Prototyping Method for Verification, Characterization and Optimization of LDPC Error Correction Systems Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikolaos Kanistras, Ahmed Mahdi, Vassilis Paliouras Special Session on FPGA-based Emulation of Hardware Architectures 2012-IC-38
Tullsen, Dean M.
2012
Efficient System Design using the Statistical Analysis of Architectural Bottlenecks Methodology Manish Arora, Feng Wang, Bob Rychlik, Dean M. Tullsen ESL Tools & Methods 2012-IC-27
Valouxis, Christos
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Special Session on  Programming Paradigms for Reconfigurable Multi-Core Embedded Systems 2012-IC-34
Velasquez, Ricardo A.
2012
BADCO : Behavioral Application-Dependent Superscalar Core Model Ricardo A. Velasquez, Pierre Michaud, Andre Seznec Embedded Simulation 2012-IC-08
Voit, Harald
2012
Challenges in Automotive Cyber-physical Systems Design Dip Goswami, Reinhard Schneider, Alejandro Masrur, Martin Lukasiewycz, Samarjit Chakraborty, Harald Voit, Anuradha Annaswamy Special Session on Aspects Of Cyber-Physical Systems 2012-IC-49
Voros, Nikolaos S.
2012
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hubner, T