SAMOS 2001
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Table of Contents SAMOS Conference 2014

Carlo Galuzzi and Alexander V. Veidenbaum Eds.

IEEE Catalog Number: CFP1452A-USB
ISBN: 978-1-4799-3769-1

Front matter










Scaling Usable Computing Capability



Tor M. Aamodt
High-Bandwidth, High-Capacity, Low-Power Memory Systems



Bruce Jacob
The Heterogeneous System Architecture: It’s beyond the GPU



Paul Blinzer

Multiprocessors & Multicores





Co-Design of Many-Accelerator Heterogeneous Systems Exploiting Virtual Platforms
1 -- 8
Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos
Robustness Analysis of Multiprocessor Schedules
9 -- 17
Shreya Adyanthaya, Zhihui Zhang, Marc Geilen, Jeroen Voeten, Twan Basten, Ramon Schiffelers
Dynamic-Vector Execution on a General Purpose EDGE Chip Multiprocessor
18 -- 25
Milovan Duric, Oscar Palomar, Aaron Smith, Milan Stanic, Osman Unsal, Adrian Cristal, Mateo Valero, Doug Burger, Alex Veidenbaum
Combining Application Adaptivity and System-wide Resource Management on Multi-Core Platforms
26 -- 33
Giuseppe Massari, Edoardo Paone, Patrick Bellasi, Gianluca Palermo, Vittorio Zaccaria, William Fornaciari, Cristina Silvano
Resource Conscious Prefetching for Irregular Applications in Multicores
34 -- 43
Muneeb Khan, Erik Hagersten



Characterizing communication behavior of dataflow programs using trace analysis
44 -- 50
Jorn W. Janneck, Simone Casale Brunet, Marco Mattavelli
On Tokens and Signals: Bridging the Semantic Gap between Dataflow Models and Hardware Implementations
51 -- 58
Stavros Tripakis, Rhishikesh Limaye, Kaushik Ravindran, Guoqiang Wang
Automated Design Flow for Coarse-Grained Reconfigurable Platforms: an RVC-CAL Multi-Standard Decoder Use-Case
59 -- 66
Carlo Sau, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale-Brunet, Marco Mattavelli



WCET-aware Scheduling Optimizations for Multi-Core Real-Time Systems
67 -- 74
Timon Kelter, Hendrik Borghorst, Peter Marwedel
A Run-Time Modulo Scheduling by using a Binary Translation Mechanism
75 -- 82
Ricardo Ferreira, Waldir Denver, Monica Pereira, Jorge Quadros, Luigi Carro, Stephan Wong

Memory Systems


Evaluating the Memory System Behavior of Smartphone Workloads
83 -- 92
Goran Narancic, Patrick Judd, Di Wu, Islam Atta, Michel Elnacouzi, Jason Zebchuck, Jorge Albericio, Natalie Enright Jerger, Andreas Moshovos, Kyros Kutulakos, Serag Gadelrab
Memory Sharing Techniques for Multi-standard High-throughput FEC Decoder
93 -- 98
Zhenzhi Wu, Dake Liu
Speculative Synchronization for Coherence-free Embedded NUMA Architectures
99 -- 106
Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy, R. Iris Bahar

Performance Analysis & Evaluation


Extended Performance Analysis of the Time Predictable On-demand Coherent Data Cache for Multi- and Many-core Systems
107 -- 114
Arthur Pyka, Mathias Rohde, Sascha Uhrig
GPGPU Workload Characteristics and Performance Analysis
115 -- 124
Sohan Lal, Jan Lucas, Michael Andersch, Mauricio Alvarez-Mesa, Ahmed Elhossini, Ben Juurlink
Performance Evaluation of the Intel Xeon Phi Manycore Architecture Using Parallel Video-Based Driver Assistance Algorithms
125 -- 132
Oliver Jakob Arndt, Daniel Becker, Florian Giesemann, Guillermo Payá-Vayá , Christopher Bartels, Holger Blume
Pre-architectural Performance Estimation for ASIP Design Based on Abstract Processor Models
133 -- 140
Juan Fernando Eusse, Christopher Williams, Luis Gabriel Murillo, Rainer Leupers, Gerd Ascheid

Architectures (Miscellanea)




Design Space Exploration for Fair Resource-Allocated NoC Architectures
141 -- 148
Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis, Dionisios Pnevmatikatos
Variable Length Instruction Compression on Transport Triggered Architectures
149 -- 155
Janne Helkala, Timo Viitanen, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Tommi Zetterman, Heikki Berg
Fast Dynamic Binary Rewriting for Flexible Thread Migration on Shared-ISA Heterogeneous MPSoCs
156 -- 163
Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, Hans Vandierendonck, Spyros Lalis
MPSoCBench: A Toolset for MPSoC System Level Evaluation
164 -- 171
Liana Duenha, Marcelo Guedes, Henrique Almeida, Matheus Boy, Rodolfo Azevedo

Power & Energy



Modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors
172 -- 180
Karel De Vogeleer, Gerard Memmi, Pierre Jouvelot, Fabien Coelho
An ESL Timing & Power Estimation and Simulation Framework for Heterogeneous SoCs
181 -- 190
Kim Grüttner, Philipp A. Hartmann, Tiemo Fandrey, Kai Hylla, Daniel Lorenz, Stefan Stattelmann, Björn Sander, Oliver Bringmann, Wolfgang Nebel, Wolfgang Rosenstiel
Evaluating Private vs. Shared Last-Level Caches for Energy Efficiency in Asymmetric Multi-Cores
191 -- 198
Anthony Gutierrez, Ronald G. Dreslinski, Trevor Mudge
Software-controlled Processor Stalls for Time and Energy Efficient Data Locality Optimization
199 -- 206
Philippe Clauss, Imen Fassi, Alexandra Jimborean

Reconfigurable Architectures


Multi-FPGA Prototyping Board Issue: the FPGA I/O Bottleneck
207 -- 214
Qingshan Tang, Habib Mehrez, Matthieu Tuna
Synthesis of Instruction Extensions on HyperCell, a Reconfigurable Datapath
215 -- 224
Kavitha T. Madhu, Saptarsi Das, C. Madhava Krishna, S. Nalesh, S. K. Nandy, Ranjani Narayan
Co-Exploration of NLA kernels and Specification of Compute Elements in Distributed Memory CGRAs 
225 -- 232
Mahesh Mahadurkar, Farhad Merchant, Arka Maity, Kapil Vatwani, Ishan Munje, Nandhini Gopalan, S. K. Nandy, Ranjani Narayan 
RuRot: Run-time Rotatable-expandable Partitions for Efficient Mapping in CGRAs
233 -- 241
Syed M. A. H. Jafri, Guilermo Serrano, Junaid Iqbal, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen

SystemC & Simultations





Asynchronous Parallel Simulation with Transaction Events
242 -- 249
Bastian Haetzer, Martin Radetzki
Highly-Parallel Special-Purpose Multicore Architecture for SystemC/TLM Simulations
250 -- 257
Nicolas Ventroux, Julien Peeters, Tanguy Sassolas, James C. Hoe
Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation
258 -- 265
Fabian Mischkalla, Wolfgang Mueller
Micro-architectural Simulation of In-order and Out-of-order ARM Microprocessors with gem5
266 -- 273
Fernando A. Endo, Damien Couroussé, Henri-Pierre Charles

Algorithms & Modeling


Ranking Software Components Using a Modified PageRank Algorithm Including Safety Aspects
274 -- 281
Dominik Reinhardt
Evaluation of Message Passing Synchronization Algorithms in Embedded Systems
282 -- 289
Lazaros Papadopoulos, Ivan Walulya, Philippas Tsigas, Dimitrios Soudris, Brendan Barry
Efficient End-to-End Latency Distribution Analysis for Probabilistic Time-Triggered Systems
290 -- 298
Mark Westmijze, Marco J. G. Bekooij, Gerard J. M. Smit
An Automotive Specific MILP Model Targeting Power-Aware Function Partitioning
299 -- 306
Gregor Walla, Andreas Herkersdorf, André S. Enger, Andreas Barthels, Hans-Ulrich Michel

Special Session on Embedded Driver Assistance Systems – Initial Results of the DESERVE Artemis-JU-project





Introduction to the Special Session on Embedded Driver Assistance Systems – Initial Results of the DESERVE Artemis-JU-project
Holger Blume
The DESERVE project: Towards future ADAS functions
308 -- 313
Matti Kutila, Pyykönen, Paul van Koningsbruggen, Nereo Pallaro, Joshué Pérez-Rastelli
A Comprehensive ASIC/FPGA Prototyping Environment for Exploring Embedded Processing Systems for Advanced Driver Assistance Applications
314 -- 321
Florian Giesemann, Guillermo Payá-Vayá, Holger Blume, Matthias Limmer, Werner Ritter
Development and Design of a Platform for Arbitration and Sharing Control Applications – a DESERVE approach –
322 -- 328
Joshué Pérez-Rastelli, David González, Fawzi Nashashibi, Fabio Tango, Nereo Pallaro, Gwenael Dunand, André Rolfsmeier
Vehicle-Hardware-In-The-Loop System for ADAS Prototyping and Validation
329 -- 334
Clément Galko, Romain Rossi, Xavier Savatier
Instruction-Set Extension for an ASIP-based SIFT Feature Extraction
335 -- 342
Nico Mentzer, Guillermo Payá-Vayá, Holger Blume, Nora von Egloffstein, Werner Ritter
Definition of an Embedded Driver Model for Driving Behavior Prediction within the DESERVE Platform
343 -- 350
Jens Klimke, Philipp Themann, Christoph Klas, Lutz Eckstein
Massively Parallel Signal Processing Challenges within a Driver Assistant Prototype Framework - First Case Study Results with a Novel MIMO-Radar
351 -- 357
Frank Meinl, Martin Kunert, Holger Blume

Special Session on Brain-targeted and brain-inspired computing




Introduction to the Special Session on Brain-targeted and brain-inspired computing
Christos Strydis
Neuronal Connectivity Assessment for Epileptic Seizure Prevention: Parallelizing the Generalized Partial Directed Coherence on Many-Core Platforms
359 -- 366
Georgios Georgis, Dionysios Reisis, Panagiotis Skordilakis, Konstantinos Tsakalis, Ashfaque Bin Shafique, George Chatzikonstantis, George Lentaris
Optimal Mapping of Inferior Olive Neuron Simulations on the Single-Chip Cloud Computer
367 -- 374
Dimitrios Rodopoulos, Giorgos Chatzikonstantis, Andreas Pantelopoulos, Dimitrios Soudris, Chris I. De Zeeuw, Christos Strydis
An analysis of dynamics of CA3b in Hippocampus
375 -- 383
Babak Keshavarz-Hedayati, Nikitas J. Dimopoulos, A. Babul