SAMOS 2001
WARNING: This section contains links to pdf files. The Adobe Acrobat Reader©, which can open these .pdf files, is available for different operative systems. To read an Acrobat file, you first download the version of Adobe Acrobat that matches your operating system. If you do not have a copy, you can download a free version for Macintosh or Windows here. If you need other versions, check out the Adobe site to find them.

Table of Contents SAMOS Conference 2012

John McAllister and Shuvra Bhattacharyya Eds.

IEEE Catalog Number: CFP1252A-ART
ISBN: 978-1-4673-2297-3

DOI: 10.1109/SAMOS.2012.6404142--10.1109/SAMOS.2012.6404203

Front matter Author Index Search

 

Keynotes

 

 

 

The Homogeneity of Architecture in a Heterogeneous world
PAGES

i

2012-IC-K1

John Goodacre
 
It's About Time
PAGES

ii

2012-IC-K2

Edward A. Lee
Maximum Performance Computing for Exascale Applications
PAGES

iii

2012-IC-K3

Oskar Mencer
       

Design Space Exploration

 

 

 

Just-in-Time Verification in ADL-based Processor Design
PAGES
1--6
 
Dominik Auras, Andreas Minwegen, Uwe Deidersen, Stefan Scurmans, Gerd Ascheid, Rainer Leupers
 
Interleaving Methods for Hybrid System-level MPSoC Design Space Exploration
PAGES
7--14
 
Roberta Piscitelli, Andy D. Pimentel
 
A Template-based Methodology for Efficient Microprocessor and FPGA Accelerator Co-Design
PAGES
15--22
 
Angeliki Kritikakou, Francky Catthoor, George S. Athanasiou, Vasilios Kelefouras, Costas Goutis 
 
Using OpenMP Superscalar for Parallelization of Embedded and Consumer Applications
PAGES
23--32
 
Michael Andersch, Chi Ching Chi, Ben Juurlink
 

Embedded Simulation

 

 

 
 
Virtual Prototyping for Efficient Multi-Core ECU Development of Driver Assistance Systems
PAGES
33--40
 
Rainer Kiesel , Martin Streubuhr, Christian Haubelt, Anestis Terzis, Jurgen Teich
 
System Modeling and Multicore Simulation Using Transactions
PAGES
41--50
 
Amine Anane, El Mostapha Aboulhamid, Yvon Savaria
 
HNOCS: Modular Open-Source Simulator for Heterogeneous NoCs
PAGES
51--57
 
Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny
 
BADCO : Behavioral Application-Dependent Superscalar Core Model
PAGES
58--67
 
Ricardo A. Velasquez, Pierre Michaud, Andre Seznec
 

Memory & Comms. Strategies

 

 

 
 
An Application-Specific Network-on-Chip for Control Architectures in RF Transceivers
PAGES
68--75
 
Siegfried Brandstatter, Mario Huemer
 
A Framework for Efficient Cache Resizing
PAGES
76--85
 
Georgios Keramidas, Chrysovalantis Datsios, Stefanos Kaxiras
 
OSR-Lite: Fast and Deadlock-Free NoC Reconfiguration Framework
PAGES
86--95
 
Alessandro Strano, Davide Bertozzi, Francisco Trivino, Jose' L. Sanchez, Francisco J. Alfaro, Jose' Flich
 
A Tightly-Coupled Multi-Core Cluster with Shared-Memory HW Accelerators
PAGES
96--103
 
Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Naser Yazdani
 

Domain-Specific Architectures

 

 

 
 
Architecture-Level Fault-Tolerance for Biomedical Implants
PAGES
104--112
 
Robert M. Seepers, Christos Strydis, Georgi N. Gaydadjiev
 
Reconfigurable Miniature Sensor Nodes for Condition Monitoring
PAGES
113--119
 
Teemu Nylanden, Jani Boutellier, Karri Nikunen, Jari Hannuksela, Olli Silven
 
Counting Stream Registers: An Efficient and Effective Snoop Filter Architecture
PAGES
120--127
 
Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne
 

Dataflow Application Synthesis

 

 

 
 
Design Space Exploration in Application-Specific Hardware Synthesis for Multiple Communicating Nested Loops
PAGES
128--135
 
Rosilde Corvino, Abdoulaye Gamatie, Marc Geilen, Lech Jozwiak
 
Automatic FPGA Synthesis of Memory Intensive C-based Kernels
PAGES
136--143
 
Matthew Milford, John McAllister
 
Throughput Driven Transformations of Synchronous Data Flows for Mapping to Heterogeneous MPSoCs
PAGES
144--151
 
Anastasia Stulova, Rainer Leupers, Gerd Ascheid
 

Dataflow Analysis

 

 

 
 
K-Periodic Schedules for Evaluating the Maximum Throughput of a Synchronous Dataflow Graph
PAGES
152--159
 
Bruno Bodin, Alix Munier-Kordon, Benoit Dupont de Dinechin
 
Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph
PAGES
160--167
 
Karol Desnos, Maxime Pelcat, Jean-Francois Nezan, Slaheddine Aridhi
 
Out-Of-Order Execution of Synchronous Data-Flow Networks
PAGES
168--175
 
Daniel Baudisch, Jens Brandt, Klaus Schneider
 

Embedded Processor Design

 

 

 
 
An Efficient Asymmetric Distributed Lock for Embedded Multiprocessor Systems
PAGES
176--182
 
Jochem H. Rutgers, Marco J.G. Bekooij, Gerard J.M. Smit
 
Simultaneous Reconfiguration of Issue-width and Instruction Cache for a VLIW Processor
PAGES
183--192
 
Fakhar Anjam, Stephan Wong, Luigi Carro, Gabriel L. Nazar, Mateus B. Rutzig
 
Energy Efficient Stream-based Configurable Architecture for Embedded Platforms
PAGES
193--200
 
Frederico Pratas, Pedro Tomas, Pedro Trancoso, Leonel Sousa
 

ESL Tools & Methods

 

 

 
 
TaBit: a Framework for Task Graph to Bitstream Generation
PAGES
201--208
 
Alessandra Bonetto, Andrea Cazzaniga, Gianluca C. Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio
 
System-on-Chip deployment with MCAPI abstraction and IP-XACT metadata
PAGES
209--216
 
Lauri Matilainen, Lasse Lehtonen, Joni-Matti Maatta, Erno Salminen, Timo D. Hamalainen
 
Efficient System Design using the Statistical Analysis of Architectural Bottlenecks Methodology
PAGES
217--226
 
Manish Arora, Feng Wang, Bob Rychlik, Dean M. Tullsen

Special Session 1 on: Programming Paradigms for Reconfigurable Multi-Core Embedded Systems

Introduction to the Special Session on: Programming Paradigms for Reconfigurable Multi-Core Embedded Systems
PAGES
227--227
Diana Gohringer and Pedro Diniz
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures
PAGES
228--235
 
Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jurgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire  
 
Adaptive Reinforcement Learning Method for Networks-on-Chip
PAGES
236--243
 
Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Pasi Liljeberg
 
Adaptive Processor Architecture
PAGES
244--251
 
Michael Huebner, Diana Goehringer, Carsten Tradowky, Joerg Henkel, Jurgen Becker
 
Adaptive dynamic memory allocators by estimating application workloads
PAGES
252--259
 
Ioannis Koutras, Alexandros Bartzas, Dimitrios Soudris
 
Hardware/Software Specialization Through Aspects: The LARA Approach
PAGES
260--267
 
Joao M. P. Cardoso, Tiago Carvalho, Joao Teixeira, Pedro C. Diniz, Fernando Goncalves, Zlatko Petrov
 
From Scilab to Multicore Embedded Systems: Algorithms and Methodologies
PAGES
268--275
 
George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Huebner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas

Special Session 2 on: FPGA-based Emulation of Hardware Architectures

 

 

 

Introduction to the Special Session on: FPGA-based Emulation of Hardware Architectures
PAGES
276--276
Holger Blume
BEE technology overview
PAGES
277--277
 
Joseph Rothman, Chen Chang
 
An FPGA-Accelerated Testbed for Hardware Component Development in MIMO Wireless Communication Systems
PAGES
278--285
 
Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
 
An FPGA-based Prototyping Method for Verification, Characterization and Optimization of LDPC Error Correction Systems
PAGES
286--293
 
Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikolaos Kanistras, Ahmed Mahdi, Vassilis Paliouras
 
A Quantitative Analysis of Fixed-Point LDPC-Decoder Implementations using Hardware-Accelerated HDL Emulations
PAGES
294--301
 
Matthias Korb, Tobias G. Noll
 
An FPGA-based Probability-aware Fault Simulator
PAGES
302--309
 
David May, Walter Stechele
 
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems
PAGES
310--317
 
Paolo Meloni, Sebastiano Pomata, Luigi Raffo, Roberta Piscitelli, Andy D. Pimentel

Special Session 3 on: Aspects Of Cyber-Physical Systems

 

 

 

Introduction to the Special Session on: Aspects Of Cyber-Physical Systems
PAGES
318--318
Ed Deprettere
Rigorous Design of Cyber-physical Systems
PAGES
319--319
 
Joseph Sifakis
 
Predictable Dynamic Embedded Data Processing
PAGES
320--327
 
Marc Geilen, Sander Stuijk, Twan Basten
 
Efficient Computing in Cyber-Physical Systems
PAGES
328--332
 
Peter Marwedel, Michael Engel
 
Is Time Predictability Quantifiable?
PAGES
333--338
 
Martin Schoeberl
 
Model-Driven Robot-Software Design using integrated Models and Co-Simulation
PAGES
339--344
 
Jan F. Broenink, Yunyun Ni
 
Multicore Enablement for Cyber Physical Systems
PAGES
345--345
 
Andreas Herkersdorf
 
Challenges in Automotive Cyber-physical Systems Design
PAGES
346--354
 
Dip Goswami, Reinhard Schneider, Alejandro Masrur, Martin Lukasiewycz, Samarjit Chakraborty, Harald Voit, Anuradha Annaswamy
 
A Co-simulation Approach for System-Level Analysis of Embedded Control Systems
PAGES
355--362
 
Michael Glass, Jurgen Teich, Liyuan Zhang
 
Instrumentation Techniques for Cyber‐Physical Systems Using the Targeted Dataflow Interchange Format
PAGES
363--363
 
Shuvra S. Bhattacharyya
 
Efficient Hardware Implementation of Data-Flow Parallel Embedded Systems
PAGES
364--371
 
Patrice Quinton, Anne-Marie Chana, Steven Derrien