SAMOS 2001
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Table of Contents SAMOS Conference 2010

Fadi J. Kurdahi and Jarmo Takala Eds.

IEEE Catalog Number: CFP1052A-PRT
ISBN: 978-1-4244-7937-5

DOI: 10.1109/ICSAMOS.2010.5642041--10.1109/ICSAMOS.2010.5642178

Front matter Author Index Search

Springer

 

Keynotes

 

 

 

Technologies for Reducing Power

PAGE

I

2010-IC-01

Trevor Mudge

VLSI Challenges to more Energy Efficient Devices

PAGE

II

2010-IC-02

Tawfik Arabi

Simulation and Modeling

 

 

 

Cycle-Accurate Performance Modelling in an Ultra-Fast Just-In-Time Dynamic Binary Translation Instruction Set Simulator

PAGES

1--10

 

Igor Bohm, Bjorn Franke, Nigel Topham

A Trace-based Scenario Database for High-level Simulation of Multimedia MP-SoCs

PAGES

11--19

 

Peter van Stralen, Andy D. Pimentel

A Library of Dual-Clock FIFOs for Cost-Effective and Flexible MPSoCs Design

PAGES

20--27

 

Alessandro Strano, Daniele Ludovici, Davide Bertozzi

Transparent Sampling

PAGES

28--36

 

Taj Muhammad Khan, Daniel Gracia-Perez, Olivier Temam

Network Processing

 

 

 

Design of a Flexible High-speed FPGA-based Flow Monitor for Next Generation Networks

PAGES

37--44

 

John McGlone, Roger Woods, Alan Marshall, Michaela Blott

A Fully Programmable FSM-based Processing Engine for Gigabytes/s Header Parsing

PAGES

45--54

 

Konstantin Septinus, Peter Pirsch, Holger Blume, Ulrich Mayer

Empirical Evaluation of Data Transformations for Network Infrastructure Applications

PAGES

55--62

 

Damon Fenacci, Bjorn Franke

Design Environment for the Support of Configurable Network Interfaces in NoC-based Platforms

PAGES

63--70

 

Amin El Mrabti, Frederic Rousseau, Frederic Petrot, Jerome Martin, Romain Lemaire, Emmanuel Vaumorin 

Image and Video Processing

 

 

 

An Efficient Realization of Forward Integer Transform in H.264/AVC Intra-frame Encoder

PAGES

71--78

 

Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov

SIMD Performance in Software Based Mobile Video Coding

PAGES

79--85

 

Tero Rintaluoma, Olli Silven

Fast Huffman Decoding by Exploiting Data Level Parallelism

PAGES

86--92

 

Tim Drijvers, Carlos Alba Pinto, Henk Corporaal, Bart Mesman

Real-Time Stereo Vision System using Semi-Global Matching Disparity Estimation: Architecture and FPGA-Implementation

PAGES

93--101

 

Christian Banz, Sebastian Hesselbarth, Holger Flatt, Holger Blume, Peter Pirsch

System-Level Design

 

 

 

Custom Multi-Threaded Dynamic Memory Management for Multiprocessor System-on-Chip Platforms

PAGES

102--109

 

Sotirios Xydis, Alexandros Bartzas, Iraklis Anagnostopoulos, Dimitrios Soudris, Kiamal Pekmestzi

Power Aware Heterogeneous MPSoC with Dynamic Task Scheduling and Increased Data Locality for Multiple Applications

PAGES

110--117

 

Oliver Arnold, Gerhard Fettweis

A System-Level Synthesis Approach from Formal Application Models to Generic Bus-Based MPSoCs

PAGES

118--125

 

Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubuhr, Jürgen Teich

Profiling and Analysis

 

 

 

ImpBench Revisited: An Extended Characterization of Implant-Processor Benchmarks

PAGES

126--135

 

Christos Strydis, Dhara Dave, Georgi N. Gaydadjiev

Efficient Static Buffering to Guarantee Throughput-Optimal FPGA Implementation of Synchronous Dataflow Graphs

PAGES

136--143

 

Hojin Kee, Shuvra S. Bhattacharyya, Jacob Kornerup

Compositional Timing Analysis

PAGES

144--151

 

Amine Marref

MP-SoC Programming

 

 

 

Programming Multi-core Architectures Using Data-Flow Techniques

PAGES

152--161

 

Samer Arandi, Paraskevas Evripidou

CLI-Based Compilation Flows for the C Language

PAGES

162--169

 

Erven Rohou, Andrea C. Ornstein, Marco Cornero

Design Space Exploration of Instruction Set Customizable MPSoCs for Multimedia Applications

PAGES

170--177

 

Unmesh D. Bordoloi, Huynh Phung Huynh, Tulika Mitra, Samarjit Chakraborty

Network-On-Chip Interconnects

 

 

 

Enhancements for Variable N-point Streaming FFT/IFFT on REDEFINE, a Runtime Reconfigurable Architecture

PAGES

178--184

 

N.Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S.K. Nandy 

On-chip Network Interfaces supporting automatic burst write creation, posted writes and read prefetch

PAGES

185--192

 

Radu Stefan, Jason de Windt, Kees Goossens

Monitor-Adapter Coupling for NOC Performance Tuning

PAGES

193--199

 

Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Kastensmidt, Altamiro Susin, Marcio Kreutz 

Compiler Techniques

 

 

 

Compile-time GPU Memory Access Optimizations

PAGES

200--207

 

Gert-Jan van den Braak, Bart Mesman, Henk Corporaal

Code Generation for a Novel STA Architecture by Using Post-Processing Backend

PAGES

208--215

 

Xiaoyan Jia, Gerhard Fettweis

Accelerating High-Level Engineering Computations by Automatic Compilation of Geometric Algebra to Hardware Accelerators

PAGES

216--222

 

Jens Huthmann, Peter Muller, Florian Stock, Dietmar Hildenbrand, Andreas Koch

OpenCL-based Design Methodology for Application-Specific Processors

PAGES

223--230

 

Pekka Jääskeläinen, Carlos S. de la Lama, Pablo Huerta, Jarmo Takala

Micro-Architecture

 

 

 

LV*: A Low Complexity Lazy Versioning HTM Infrastructure

PAGES

231--240

 

Anurag Negi, M. M. Waliullah, Per Stenstrom

A Polymorphic Register File for Matrix Operations

PAGES

241--249

 

Catalin Ciobanu, Georgi Kuzmanov, Georgi N. Gaydadjiev, Alex Ramirez

Interleaving Granularity on High Bandwidth Memory Architecture for CMPs

PAGES

250--257

 

Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex Ramirez

Automatic Port and Bus Sizing in NoGAP

PAGES

258--264

 

Per Karlström, Wenbiao Zhou, Dake Liu

Design Space Exploration

 

 

 

Design Space Exploration of Systolic Realization of QR Factorization on a Runtime Reconfigurable Platform

PAGES

265--272

 

Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S.K. Nandy

Energy-Aware Design Space Exploration of RegisterFile for Extensible Processors

PAGES

273--281

 

Amir Yazdanbakhsh, Mehdi Kamal, Mostafa E. Salehi, Hamid Noori, Sied Mehdi Fakhraie

Exploring the Unified Design-Space of Custom-Instruction Selection and Resource Sharing

PAGES

282--291

 

Marcela Zuluaga, Nigel Topham

Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR)

 

 

 

Introduction to the Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR)

PAGE

292

 

John Glossner

A GPU Implementation for two MIMO–OFDM Detectors

PAGES

293--300

 

Teemu Nylanden, Janne Janhunen, Olli Silven, Markku Juntti

CORDIC-Based LMMSE Equalizer for Software Defined Radio

PAGES

301--308

 

Murugappan Senthilvelan, Javier Hormigo, Joon Hwa Chun, Mihai Sima, Daniel Iancu, Michael Schulte, John Glossner 

On the Scalability of SIMD Processing for Software Defined Radio Algorithms

PAGES

309--317

 

Peter Westermann, Hartmut Schröder

SDR Platform for 802.11n and 3-GPP LTE

PAGES

318--323

 

Jeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre 

ARAL-CR: An Adaptive Reasoning and Learning
Cognitive Radio Platform

PAGES

324--331

 

Sao-Jie Chen, Pao-Ann Hsiung, Chu Yu, Mao-Hsu Yen, Sakir Sezer, Michael Schulte, Yu-Hen Hu 

Special Session on Multicore Architectures for Embedded Systems

 

 

 

Introduction to the Special Session on Multicore Architectures for Embedded Systems

PAGE

332

2010-IC-44

Luigi Carro, Stephan Wong

Exploration Framework for Run-Time Resource Management of Embedded Multi-Core Platforms

PAGES

333--340

 

Ch. Ykman-Couvreur

Towards Scalable I/O on a Many-core Architecture

PAGES

341--348

 

Michael A. Hicks, Hicks Michiel, W. van Tol, Chris R. Jesshope

Embedded Multicore Architectures for LDPC Decoding

PAGES

349--356

 

Gabriel Falcao, Leonel Sousa, Vitor Silva

Message Passing Interface Support for the Runtime Adaptive Multi-Processor System-on-Chip RAMPSoC

PAGES

357--364

 

Diana Gohringer, Michael Hubner, Laure Hugot-Derville, Jürgen Becker

Designing and Validating Access Policies to Reconfigurable Resources in Multiprocessor Systems on Chip

PAGES

365--371

 

Fabio Arlati, Francesco Bruschi, Donatella Sciuto

Identifying Communication Models in Process Networks derived from Weakly Dynamic Programs

PAGES

372--379

 

Dmitry Nadezhkin, Todor Stefanov