SAMOS 2001
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Table of Contents SAMOS Conference 2009

Walid Najjar and Michael J. Schulte Eds.

IEEE Catalog Number: CFP0952A-PRT
ISBN: 978-1-4244-4501-1
Library of Congress: 2009903596

DOI: 10.1109/ICSAMOS.2009.5289220--10.1109/ICSAMOS.2009.5289259

Front matter Author Index Search

Springer

 

Keynotes

 

 

 

Mobile visual computing

PAGE

i

2009-IC-01

K. Pulli

“Slower than you think” — The evolution of processor and SoC architectures

PAGE

ii

2009-IC-02

G. Martin

Reconfigurable Systems

 

 

 

A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA

PAGES

1--8

 

R.J. Aliaga, R. Gadea, R.J. Colom, J. Cerda, N. Ferrando, V. Herrero 

High-speed FPGA-based implementations of a Genetic Algorithm

PAGES

9--16

 

M. Vavouras, K. Papadimitriou, I. Papaefstathiou

OpenMP extensions for FPGA accelerators

PAGES

17--24

 

D. Cabrera, Xavier Martorell, Georgi N. Gaydadjiev, Eduard Ayguade, D. Jimenez-Gonzalez

High-level synthesis for the design of FPGA-based signal processing systems

PAGES

25--32

 

E. Casseau, B. Le Gal

Instruction Scheduling and Microarchitecture Optimizations

 

 

 

Instruction scheduling for VLIW processors under variation scenario

PAGES

33--40

 

N.V. Mujadiya

A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors

PAGES

41--48

 

E. Safi, A. Moshovos, A. Veneris

Instruction-based reuse-distance prediction for effective cache management

PAGES

49--58

 

Pavlos Petoumenos, Georgios Keramidas, Stefanos Kaxiras

Simulation and Emulation Techniques

 

 

 

Adaptive simulation sampling using an Autoregressive framework

PAGES

59--66

 

S. Daruwalla, R. Sendag, J. Yi

An emulation-based real-time power profiling unit for embedded software

PAGES

67--73

 

A. Genser, C. Bachmann, J. Haid, C. Steger, R. Weiss

A timed HW/SW coemulation technique for fast yet accurate system verification

PAGES

74--81

 

Hoeseok Yang, Youngmin Yi, Soonhoi Ha

RETHROTTLE: Execution throttling in the REDEFINE SoC architecture

PAGES

82--91

 

A.N. Satrawala, S.K. Nandy

Multiprocessor Modeling and Evaluation

 

 

 

Generation and calibration of compositional performance analysis models for multi-processor systems

PAGES

92--99

 

W. Haid, M. Keller, Huang Kai, I. Bacivarov, L. Thiele

Performance evaluation of concurrently executing parallel applications on multi-processor systems

PAGES

100--107

 

Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal

Manycore performance analysis using timed configuration graphs

PAGES

108--117

 

J. Bengtsson, B. Svensson

Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques

PAGES

118--124

 

G. Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria

Multiprocessor Communication and Synchronization

 

 

 

Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures

PAGES

125--132

 

Holger Flatt, I. Schmadecke, M. Kargel, Holger Blume, Peter Pirsch

Synchronization on heterogeneous multiprocessor systems

PAGES

133--139

 

Mayan Moudgill, V. Kalashnikov, Murugappan Senthilvelan, U. Srikantiah, Li Tak-po, P. Balzola, John Glossner 

Inter-task communication via overlapping read and write windows for deadlock-free execution of cyclic task graphs

PAGES

140--148

 

T. Bijlsma, Marco J.G. Bekooij, Gerard J. M. Smit

FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability

PAGES

149--156

 

G. Kalokerinos, V. Papaefstathiou, G. Nikiforos, S. Kavadias, Manolis G.H. Katevenis, D. Pnevmatikatos, Yang Xiaojun 

Architectures and Implementations

 

 

 

High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures

PAGES

157--164

 

G. Garga, David Guevorkian, S.K. Nandy, H.S. Jamadagni

Novel energy-efficient scalable soft-output SSFE MIMO detector architectures

PAGES

165--171

 

R. Fasthuber, Li Min, David Novo, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor 

Customizing wide-SIMD architectures for H.264

PAGES

172--179

 

S. Seo, Mark Woh, Scott Mahlke, Trevor Mudge, S. Vijay, Chaitali Chakrabarti 

Parallel implementation of convolution encoder for software defined radio on DSP architecture

PAGES

180--186

 

Jui-Chieh Lin, Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen, Yu-Hen Hu