SAMOS 2001
WARNING: This section contains links to pdf files. The Adobe Acrobat Reader©, which can open these .pdf files, is available for different operative systems. To read an Acrobat file, you first download the version of Adobe Acrobat that matches your operating system. If you do not have a copy, you can download a free version for Macintosh or Windows here. If you need other versions, check out the Adobe site to find them.

Table of Contents SAMOS Conference 2008

Walid Najjar and Holger Blume Eds.

IEEE Catalog Number: CFP0852A-PRT
ISBN: 978-1-4244-1985-2
Library of Congress: 2007943034

DOI: 10.1109/ICSAMOS.2008.4664829--10.1109/ICSAMOS.2008.4664868

Front matter Author Index Search

 

Keynotes

 

 

 

PicoServer - Building a Compact Energy Efficient Multiprocessor

PAGE

i

2008-IC-01

Trevor Mudge

Challenges in Embedded System Simulation

PAGE

ii

2008-IC-02

Tor Jeremiassen

Towards Unified Mechanisms for Inter-Processor Communication

PAGE

iii

2008-IC-03

Manolis G.H. Katevenis

Embedded Parallel Systems

 

 

 

A General Model of Concurrency and its Implementation as Many-core Dynamic RISC Processors

PAGES

1--9

 

Thomas A. M. Bernard, K. Bousias, L. Guang, Chris R. Jesshope, M. Lankamp, M. W. van Tol, L. Zhang 

A Parameterized Dataflow Language Extension for Embedded Streaming Systems

PAGES

10--17

 

Yuan Lin, Yoonseo Choi, Scott Mahlke, Trevor Mudge, Chaitali Chakrabarti

An Architecture for the Simultaneous Execution of Hard Real-Time Threads

PAGES

18--24

 

Jonathan Barre, Christine Rochange, Pascal Sainrat

An Adaptive Bloom Filter Cache Partitioning Scheme for Multicore Architectures

PAGES

25--32

 

Konstantinos Nikas, Matthew Horsnell, Jim Garside

Network on a Chip

 

 

 

On Brain-inspired Hybrid Topologies for Nano-architectures – A Rent’s Rule Approach –

PAGES

33--40

 

Valeriu Beiu, Basheer A. M. Madappuram, Martin McGinnity

Realizing Reconfigurable Mesh Algorithms on Softcore Arrays

PAGES

41--48

 

Heiner Giefers, Marco Platzner

A Light–Weight Network–on–Chip Architecture for Dynamically Reconfigurable Systems

PAGES

49--56

 

Simone Corbetta, Vincenzo Rana, Marco Domenico Santambrogio, Donatella Sciuto

Design Space Exploration

 

 

 

Systematic Design Space Exploration for Customisable Multi-Processor Architectures

PAGES

57--64

 

Ben Cope, Peter Y.K. Cheung, Wayne Luk

A Clustering Method for the Identification of Convex Disconnected Multiple Input Multiple Output Instructions

PAGES

65--73

 

Carlo Galuzzi, Dimitris Theodoropoulos, Koen Bertels

Multi-Objective Routing and Topology Optimization in Networked Embedded Systems

PAGES

74--81

 

Michael Glass, Martin Lukasiewycz, Rolf Wanka, Christian Haubelt, Jürgen Teich

Applications

 

 

 

ImpBench: A novel benchmark suite for biomedical, microelectronic implants

PAGES

82--91

 

Christos Strydis, Christoforos Kachris, Georgi N. Gaydadjiev

Perceptual Feature based Music Classification - A DSP Perspective for a New Type of Application

PAGES

92--99

 

Holger Blume, M. Haller, Martin Botteck, W. Theimer

Software Defined Radio Implementation of K-best List Sphere Detector Algorithm

PAGES

100--107

 

Janne Janhunen, Olli Silven, Markku Juntti, Markus Myllylä

Processor Architecture

 

 

 

Fine-grained Application-speci c Instruction Set Processor Design for the K-best List Sphere Detector Algorithm

PAGES

108--115

 

Juho Antikainen, Perttu Salmela, Olli Silven, Markku Juntti, Jarmo Takala, Markus Myllylä 

An Instruction Set Extension for Java Bytecodes Translation Acceleration

PAGES

116--123

 

Isidoros Sideris, Kiamal Pekmestzi, George Economakos

Architectural and Algorithm level Fault Tolerant Techniques for Low Power High Yield Multimedia Devices

PAGES

124--131

 

Mohammad A. Makhzan (Avesta Sasan), Ahmed Eltawil, Fadi J. Kurdahi

Comparative Architectural Characterization of SPEC CPU2000 and CPU2006 Benchmarks on the Intel Core 2 Duo Processor

PAGES

132--141

 

Arun Kejariwal, Alexander V. Veidenbaum, Xinmin Tian, Milind Girkar, Utpal Banerjee

Multiprocessors

 

 

 

Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems

PAGES

142--149

 

Antonino Tumeo, Christian Pilato, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi

An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods

PAGES

150--157

 

Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria

Efficient Management of Speculative Data in Hardware Transactional Memory Systems

PAGES

158--164

 

M. M. Waliullah, Per Stenstrom

An Intermediate Format for Automatic Generation of MPSoC Virtual Prototypes

PAGES

165--172

 

Alexandre Chureau, Frederic Petrot

Reconfigurable Computing

 

 

 

Exploiting Partial Reconfiguration for Flexible Software Debugging

PAGES

173--181

 

Giovanni Busonera, Alessandro Forin, Richard Neil Pittman

A Cost Model for Partial Dynamic Reconfiguration

PAGES

182--186

 

Markus Rullmann, Renate Merker

Reconfigurable Design with Clock Gating

PAGES

187--194

 

W.G. Osborne, Wayne Luk, J. G. F. Coutinho, O. Mencer

Memory and Caches

 

 

 

A Centralized Cache Miss Driven Technique to Improve Processor Power Dissipation

PAGES

195--202

 

Houman Homayoun, Mohammad Makhzan, Jean-Luc Gaudiot, Alexander V. Veidenbaum

A Priority-Expression-Based Burst Scheduling of Memory Reordering Access

PAGES

203--209

 

Jun Pang, Lei Yang, Lei Shi, Tiejun Zhang, Donghui Wang, Chaohuan Hou 

Improving Memory Subsystem Performance in Network Processors with Smart Packet Segmentation

PAGES

210--217

 

Kimon Karras, Daniel Llorente, Thomas Wild, Andreas Herkersdorf

Improving TLB Energy for Java Applications on JVM

PAGES

218--223

 

Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee