SAMOS 2001
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Table of Contents SAMOS Conference 2007

Holger Blume, Georgi Gaydadjiev, John Glossner, Peter Knijnenburg Eds.

IEEE Catalog Number: 07EX1707
ISBN: 1-4244-1058-4
Library of Congress: 2007921420

DOI: 10.1109/ICSAMOS.2007.4285719--10.1109/ICSAMOS.2007.4285754

Front matter Author Index Search

 

Processor Architectures

 

 

 

Applying Data Mapping Techniques to Vector DSPs

PAGES

1--8

2007-IC-01

Peter Westermann, L. Schwoerer, A. Kaufmann

Instruction Set Encoding Optimization for Code Size Reduction

PAGES

9--17

2007-IC-02

M. Med, A. Krall

FlexCore: Utilizing Exposed Datapath Control for Effcient Computing

PAGES

18--25

2007-IC-03

M. Thuresson, M. Sjalander, M. Bjork, L. Svensson, P. Larsson-Edefors, Per Stenstrom 

Prototyping Effcient Interprocessor Communication Mechanisms

PAGES

26--33

2007-IC-04

V. Papaefstathiou, D. Pnevmatikatos, M. Marazakis, G. Kalokairinos, A. Ioannou, M. Papamichael, S. Kavadias, G. Mihelogiannakis, Manolis G.H. Katevenis

Design Space Exploration

 

 

 

Design Space Exploration of Configuration Manager for Network Processing Applications

PAGES

34--40

2007-IC-05

Christoforos Kachris, Stamatis Vassiliadis

Design Space Exploration of Media Processors: A Parameterized Scheduler

PAGES

41--49

2007-IC-06

Guillermo Payá Vayá, J. Martin-Langerwerf, P. Taptimthong, Peter Pirsch

Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration

PAGES

50--57

2007-IC-07

Lee Ganghee, Lee Seokhyun, Ahn Yongjin, Choi Kiyoung

Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems

PAGES

58--65

2007-IC-08

L. Papadopoulos, C. Baloukas, N. Zompakis, Dimitrios Soudris

Multiprocessor Architectures

 

 

 

On the Problem of Minimizing Workload Execution Time in SMT processors

PAGES

66--73

2007-IC-09

F.J. Cazorla, Peter M. W. Knijnenburg, R. Sakellariou, E. Fernandez, Alex Ramirez, Mateo Valero 

Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform

PAGES

74--81

2007-IC-10

Holger Blume, J.v. Livonius, L. Rotenberg, Tobias G. Noll, H. Bothe, Jörg Brakensiek 

An Interrupt Controller for FPGA-based Multiprocessors

PAGES

82--87

2007-IC-11

Antonino Tumeo, M. Branca, L. Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto 

Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems

PAGES

88--95

2007-IC-12

N. Saint-Jean, Pascal Benoit, Gilles Sassatelli, L. Torres, Michel Robert

Systems and Applications

 

 

 

A Hardware/Software Architecture for Tool Path Computation. An Application to Turning Lathe Machining

PAGES

96--102

2007-IC-13

S. Cuenca, A. Martinez, A. Jimeno, J.L. Sanchez

Energy effciency of mobile video decoding

PAGES

103--109

2007-IC-14

Tero Rintaluoma, Olli Silven

Instruction-Level Fault Tolerance Configurability

PAGES

110--117

2007-IC-15

Demid Borodin, Ben Juurlink, Stamatis Vassiliadis

The Weight-Watcher Service and its Lightweight Implementation

PAGES

118--127

2007-IC-16

B. Garbinato, R. Guerraoui, J. Hulaas, A. Kounine, M. Monod, J.H. Spring 

Reconfigurable Architectures

 

 

 

COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable Systems

PAGES

128--136

2007-IC-17

Wu Kehuai, J. Madsen

Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme

PAGES

137--144

2007-IC-18

S. Xydis, George Economakos, Kiamal Pekmestzi

An Evolutionary Approach to Area-Time Optimization of FPGA designs

PAGES

145--152

2007-IC-19

Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo 

The ARISE Reconfigurable Instruction Set Extensions Framework

PAGES

153--160

2007-IC-20

N. Vassiliadis, G. Theodoridis, S. Nikolaidis

Memory Architectures and Memory Optimization

 

 

 

Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow

PAGES

161--168

2007-IC-21

J. Keinert, Christian Haubelt, Jürgen Teich

Online Prediction of Applications Cache Utility

PAGES

169--177

2007-IC-22

M. Moreto, F.J. Cazorla, Alex Ramirez, Mateo Valero

Maximum and Sorted Cache Occupation Using Array Padding

PAGES

178--185

2007-IC-23

E. Herruzo, E.L. Zapata, O. Plata

A Memory-Effcient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems

PAGES

186--193

2007-IC-24

V. Dimopoulos, I. Papaefstathiou, D. Pnevmatikatos

Cryptography

 

 

 

A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications

PAGES

194--200

2007-IC-25

N. Mentens, K. Sakiyama, L. Batina, B. Preneel, I. Verbauwhede

Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity Machines

PAGES

201--208

2007-IC-26

S. Muhlbach, S. Wallner

A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies

PAGES

209--214

2007-IC-27

F. Regazzoni, S. Badel, T. Eisenbarth, Johann Großschädl, A. Poschmann, Z. Toprak, M. Macchetti, Laura Pozzi, C. Paar, Y.  Leblebici, Paolo Ienne