SAMOS 2001
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Table of Contents SAMOS Workshop 2005

Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala and Stamatis Vassiliadis Eds.
Lecture Notes in Computer Science
Volume 3553, 2005, DOI: 10.1007/b138322

Front matter Author Index Search

Springer

 

Keynote

 

 

 

Platform Thinking in Embedded Systems

PAGE

1

2005-WS-01

Bob Iannucci

Reconfigurable System Design and Implementations

 

 

 

Interprocedural Optimization for Dynamic Hardware Configurations

PAGES

2--11

 

Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis

Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques

PAGES

12--21

 

M. Glesner, H. Hinkelmann, T. Hollstein, L. S. Indrusiak, T. Murgan, A.M. Obeid, M. Petrov, T. Pionteck, P. Zipf

Reconfigurable Multiple Operation Array

PAGES

22--31

 

Humberto Calderón, Stamatis Vassiliadis

RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration

PAGES

32--40

 

Guillermo Payá Vayá, Javier Martín Langerwerf, Peter Pirsch

Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping

PAGES

41--50

 

Ricardo Ferreira, João M. P. Cardoso, Andre Toledo, Horácio C. Neto

Automatic FIR Filter Generation for FPGAs

PAGES

51--61

 

Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich

Two-Dimensional Fast Cosine Transform for Vector-STA Architectures

PAGES

62--71

 

J. P. Robelly, A. Lehmann, Gerhard Fettweis

Configurable Computing for High-Security/High-Performance Ambient Systems

PAGES

72--81

 

Guy Gogniat, Wayne Burleson, Lilian Bossuet

FPL-3E: Towards Language Support for Reconfigurable Packet Processing

PAGES

82--92

 

Mihai Lucian Cristea, Claudiu Zissulescu, Ed F. Deprettere, Herbert Bos

Processor Architectures, Design and Simulation

 

 

 

Flux Caches: What Are They and Are They Useful?

PAGES

93--102

 

Georgi N. Gaydadjiev, Stamatis Vassiliadis

First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption

PAGES

103--111

 

Cheol Hong Kim, Sunghoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon

A Novel JAVA Processor for Embedded Devices

PAGES

112--121

 

Yiyu Tan, Chihang Yau, Kaiman Lo, Paklun Mok, Anthony S. Fong

Formal Specification of a Protocol Processor

PAGES

122--131

 

Tomi Westerlund, Juha Plosila

Tuning a Protocol Processor Architecture Towards DSP Operations

PAGES

132--141

 

Jani Paakkulainen, Seppo Virtanen, Jouni Isoaho

Observations on Power-Efficiency Trends in Mobile Communication Devices

PAGES

142--151

 

Olli Silven, Kari Jyrkkä

CORDIC-Augmented Sandbridge Processor for Channel Equalization

PAGES

152--161

 

Mihai Sima, John Glossner, Daniel Iancu, Hua Ye, Andrei Iancu, A. Joseph Hoane 

Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic

PAGES

162--171

 

Sunghoon Shim, Jong Wook Kwak, Cheol Hong Kim, Sung Tae Jhang, Chu Shik Jhon

Exploiting Intra-function Correlation with the Global History Stack

PAGES

172--181

 

Fei Gao, Suleyman Sair

Power Efficient Instruction Caches for Embedded Systems

PAGES

182--191

 

Dinesh C. Suresh, Walid A. Najjar, Jun Yang

Micro-architecture Performance Estimation by Formula

PAGES

192--201

 

Lucanus J. Simonson, Lei He

Offline Phase Analysis and Optimization for Multi-configuration Processors

PAGES

202--211

 

Frederik Vandeputte, Lieven Eeckhout, Koen De Bosschere

Hardware Cost Estimation for Application-Specific Processor Design

PAGES

212--221

 

Teemu Pitkänen, Tommi Rantanen, Andrea Cilio, Jarmo Takala

Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures

PAGES

222--231

 

Stefan Farfeleder, Andreas Krall, Nigel Horspool

Generating Stream Based Code from Plain C

PAGES

232--241

 

Marcel Beemster, Hans van Someren, Liam Fitzpatrick, Ruben van Royen

Fast Real-Time Job Selection with Resource Constraints Under Earliest Deadline First

PAGES

242--250

 

Sangchul Han, Moonju Park, Yookun Cho

A Programming Model for an Embedded Media Processing Architecture

PAGES

251--261

 

Dan Zhang, Zeng-Zhi Li, Hong Song, Long Liu

Automatic ADL-Based Assembler Generation for ASIP Programming Support

PAGES

262--268

 

Leonardo Taglietti, José O. Carlomagno Filho, Daniel C. Casarotto, Olinto J. V. Furtado, Luiz C. V. dos Santos

Sandbridge Software Tools

PAGES

269--278

 

John Glossner, Sean Dorward, Sanjay Jinturkar, Mayan Moudgill, Erdem Hokenek, Michael Schulte, Stamatis Vassiliadis 

Architectures and Implementations

 

 

 

A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems

PAGES

279--288

 

Philippe Marchand, Purnendu Sinha

Pattern Matching Acceleration for Network Intrusion Detection Systems

PAGES

289--298

 

Sunil Kim

Real-Time Stereo Vision on a Reconfigurable System

PAGES

299--307

 

SungHwan Lee, Jongsu Yi, JunSeong Kim

Application of Very Fast Simulated Reannealing (VFSR) to Low Power Design

PAGES

308--313

 

Ali Manzak, Huseyin Goksu

Compressed Swapping for NAND Flash Memory Based Embedded Systems

PAGES

314--323

 

Sangduck Park, Hyunjin Lim, Hoseok Chang, Wonyong Sung

A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms

PAGES

324--333

 

David Guevorkian, Petri Liuha, Aki Launiainen, Konsta Punkka, Ville Lappalainen

A Scalable Embedded JPEG2000 Architecture

PAGES

334--343

 

Chunhui Zhang, Yun Long, Fadi J. Kurdahi

A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design

PAGES

344--353

 

Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan

Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context

PAGES

354--363

 

Erno Salminen, Tero Kangas, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, Timo D. Hämäläinen 

DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor

PAGES

364--373

 

Kyriakos Stavrou, Paraskevas Evripidou, Pedro Trancoso

System Level Design, Modeling and Simulation

 

 

 

Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets

PAGES

374--383

 

Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll

High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks

PAGES

384--393

 

Mauri Kuorilehto, Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen

The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models

PAGES

394--403

 

Maziar Goudarzi, Shaahin Hessabi

Design and Implementation of a WLAN Terminal Using UML 2.0 Based Design Flow

PAGES

404--413

 

Petri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen

Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms

PAGES

414--423

 

John McAllister, Roger Woods, D. Reilly, Scott Fischaber, R. Hasson

DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context

PAGES

424--433

 

P. Bomel, N. Abdelli, E. Martin, A.-M. Fouilliart, E. Boutillon, P. Kajfasz 

SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC

PAGES

434--444

 

Sören Sonntag, Matthias Gries, Christian Sauer

Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications

PAGES

445--454

 

Marijn Temmerman, Edgar G. Daylight, Francky Catthoor, Serge Demeyer, Tom Dhaene

A Case for Visualization-Integrated System-Level Design Space Exploration

PAGES

455--464

 

Andy D. Pimentel

Mixed Virtual/Real Prototypes for Incremental System Design – A Proof of Concept

PAGES

465--474

 

Stefan Eilers, C. Müller-Schloer