SAMOS 2001
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Table of Contents SAMOS Workshop 2004

Andy D. Pimentel and Stamatis Vassiliadis Eds.
Lecture Notes in Computer Science
Volume 3133, 2004, DOI: 10.1007/b98714

Front matter Author Index

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Springer

 

Keynote

 

 

 

Programming Extremely Flexible Platforms -- Keynote Speech

PAGE

191

2004-WS-01

Kees Vissers

Reconfigurable Computing

 

 

 

The Virtex II Pro MOLEN Processor

PAGES

192--202

 

Georgi Kuzmanov, Georgi N. Gaydadjiev, Stamatis Vassiliadis

Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements

PAGES

203--212

 

Dirk Stroobandt, Hendrik Eeckhaut, Harald Devos, Mark Christiaens, Fabio Verdicchio, Peter Schelkens 

Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques

PAGES

213--223

 

Pedro C. Diniz

Modeling Loop Unrolling: Approaches and Open Issues

PAGES

224--233

 

João M. P. Cardoso, Pedro C. Diniz

Self-loop Pipelining and Reconfigurable Dataflow Arrays

PAGES

234--243

 

João M. P. Cardoso

Architecture Exploration for 3G Telephony Applications Using a Hardware–Software Prototyping Platform

PAGES

244--253

 

François Charot, Madeleine Nyamsi, Patrice Quinton, Charles Wagner

Embedded Context Aware Hardware Component Generation for Dataflow System Exploration

PAGES

254--263

 

John McAllister, Roger Woods, Richard Walke

On the (Re-)Use of IP-Components in Re-configurable Platforms

PAGES

264--273

 

Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere

Customising Hardware Designs for Elliptic Curve Cryptography

PAGES

274--283

 

Nicolas Telle, Wayne Luk, Ray C. C. Cheung

Dynamic Hardware Reconfigurations: Performance Impact for MPEG2

PAGES

284--292

 

Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis

Compiler and System Techniques for soc Distributed Reconfigurable Accelerators

PAGES

293--302

 

Joël Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, Samar Yazdani 

Architectures and Implementation

 

 

 

Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications

PAGES

303--312

 

Júlio C. B. Mattos, Antonio Carlos S. Beck, Luigi Carro, Flávio R. Wagner

On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering

PAGES

313--322

 

Michael Hosemann, Gerhard Fettweis

Memory Bandwidth Requirements of Tile-Based Rendering

PAGES

323--332

 

Iosif Antochi, Ben Juurlink, Stamatis Vassiliadis, Petri Liuha

Using CoDeL to Rapidly Prototype Network Processsor Extensions

PAGES

333--342

 

Nainesh Agarwal, Nikitas J. Dimopoulos

Synchronous Transfer Architecture (STA)

PAGES

343--352

 

Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matúš, Marcus Bronzel, Gerhard Fettweis 

Generated DSP Cores for Implementation of an OFDM Communication System

PAGES

353--362

 

Hendrik Seidel, Emil Matúš, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard Fettweis 

A Novel Data-Path for Accelerating DSP Kernels

PAGES

363--372

 

Michalis D. Galanis, G. Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis

Scalable FFT Processors and Pipelined Butterfly Units

PAGES

373--382

 

Jarmo Takala, Konsta Punkka

Scalable Instruction-Level Parallelism

PAGES

383--392

 

Chris R. Jesshope

A Low-Power Multithreaded Processor for Baseband Communication Systems

PAGES

393--402

 

Michael Schulte, John Glossner, Suman Mamidi, Mayan Moudgill, Stamatis Vassiliadis

Initial Evaluation of Multimedia Extensions on VLIW Architectures

PAGES

403--412

 

Esther Salamí, Mateo Valero

HIBI v.2 Communication Network for System-on-Chip

PAGES

413--422

 

Erno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen 

System Modeling  and Simulation

 

 

 

DIF: An Interchange Format for Dataflow-Based Design Tools

PAGES

423--432

 

Chia-Jui Hsu, Fuat Keceli, Ming-Yung Ko, Shahrooz Shahparnia, Shuvra S. Bhattacharyya

Scalable and Modular Scheduling

PAGES

433--442

 

Paul Feautrier

Early ISS Integration into Network-on-Chip Designs

PAGES

443--452

 

Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr 

Cycle Accurate Simulation Model Generation for SoC Prototyping

PAGES

453--462

 

Antoine Fraboulet, Tanguy Risset, Antoine Scherrer

Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting

PAGES

463--473

 

Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun 

A Communication-Centric Design Flow for HIBI-Based SoCs

PAGES

474--483

 

Tero Kangas, Jouni Riihimäki, Erno Salminen, Vesa Lahtinen, Heikki Orsila, Kimmo Kuusilinna, Timo D. Hämäläinen 

Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets

PAGES

484--493

 

Holger Blume, Thorsten von Sydow, Tobias G. Noll

Communication Optimization in Compaan Process Networks

PAGES

494--506

 

Ioan Cimpian, Alexandru Turjan, Ed F. Deprettere, Erwin de Kock

Analysis of Dataflow Programs with Interval-Limited Data-Rates

PAGES

507--518

 

Jürgen Teich, Shuvra S. Bhattacharyya

High-Speed Event-Driven RTL Compiled Simulation

PAGES

519--529

 

Alexey Kupriyanov, Frank Hannig, Jürgen Teich

A High-Level Programming Paradigm for SystemC

PAGES

530--539

 

Mark Thompson, Andy D. Pimentel

Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications

PAGES

540--549

 

Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis 

Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration

PAGES

550--559

 

Laurenţiu Nicolae, Ed F. Deprettere