SAMOS XII - Final Program (PDF)
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*** Abstract in Proceedings
SUNDAY JULY 15, 2012
9:00 - 13:30 TUTORIAL ON EMBEDDED RECONFIGURABLE ARCHITECTURES
Organized by: Luigi Carro (UFRGS, Br), Roberto Giorgi (UNISI, IT), Stamatis Kavvadias (UNISI, IT), Stefanos Kaxiras (UU, SE), Georgios Keramidas (ISI, Gr), Francesco Papariello (STMICRO, It), Claudio Scordino (EVI, It), Stephan Wong (TUD, Nl)
9:00 - 11:00 TUTORIAL ON EMBEDDED RECONFIGURABLE ARCHITECTURES, Part 1
11:00 - 11:30 COFFEE BREAK
11:30 - 13:30 TUTORIAL ON EMBEDDED RECONFIGURABLE ARCHITECTURES, Part 2
13:30     END OF THE TUTORIAL
 
MONDAY JULY 16, 2012
8:30 - 8:50 OPENING (Auditorium)
Shuvra Bhattacharyya, University of Maryland, US -- John McAllister, Queen's University of Belfast, UK 
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8:50 - 9:40   SESSION: Design Space Exploration 8:50 - 9:40   SESSION: Embedded Simulation 8:50 - 9:40   SESSION: Memory & Comms. Strategies
Chair: Hartwig Jeschke, Leibniz University Hannover, DE Chair: Carlo Galuzzi, Delft University of Technology, NL Chair: John Glossner, Optimum Semiconductor Technologies, US
8:50 - 9:10 13 Just-in-Time Verification in ADL-based Processor Design 8:50 - 9:10 5 Virtual Prototyping for Efficient Multi-Core ECU Development of Driver Assistance Systems 8:50 - 9:10 4 An Application-Specific Network-on-Chip for Control Architectures in RF Transceivers
Dominik Auras, Andreas Minwegen, Uwe Deidersen, Stefan Scurmans, Gerd Ascheid, Rainer Leupers Rainer Kiesel, Martin Streubuhry, Christian Haubeltz, Anestis Terzis, Jurgen Teich Siegfried Brandstatter, Mario Huemer
9:15 - 9:35 78 Interleaving Methods for Hybrid System-level MPSoC Design Space Exploration 9:15 - 9:35 22 System Modeling and Multicore Simulation Using Transactions 9:15 - 9:35 16 A Framework for Efficient Cache Resizing
Roberta Piscitelli, Andy D. Pimentel Amine Anane, El Mostapha Aboulhamid, Yvon Savaria Georgios Keramidas, Chrysovalantis Datsios, Stefanos Kaxiras
9:40 - 10:00 COFFEE BREAK
10:00 - 10:50   SESSION: Design Space Exploration 10:00 - 10:50   SESSION: Embedded Simulation 10:00 - 10:50   SESSION: Memory & Comms. Strategies
Chair: Hartwig Jeschke, Leibniz University Hannover, DE Chair: Carlo Galuzzi, Delft University of Technology, NL Chair: John Glossner, Optimum Semiconductor Technologies, US
10:00 - 10:20 9 A Template-based Methodology for Efficient Microprocessor and FPGA Accelerator Co-Design 10:00 - 10:20 25 HNOCS: Modular Open-Source Simulator for Heterogeneous NoCs 10:00 - 10:20 54 OSR-Lite: Fast and Deadlock-Free NoC Reconfiguration Framework
Angeliki Kritikakou, Francky Catthoor, George S. Athanasiou, Vasilios Kelefouras, Costas Goutis  Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny Alessandro Strano, Davide Bertozzi, Francisco Trivino, Jose L. Sanchez, Francisco J. Alfaro, Jose Flich
10:25 - 10:45 1 Using OpenMP Superscalar for Parallelization of Embedded and Consumer Applications 10:25 - 10:45 27 BADCO : Behavioral Application-Dependent Superscalar Core Model 10:25 - 10:45 62 A Tightly-Coupled Multi-Core Cluster with Shared-Memory HW Accelerators
Michael Andersch, Chi Ching Chi, Ben Juurlink Ricardo A. Velasquez, Pierre Michaud, Andre Seznec Masoud Dehyadegari, Andrea Marongiu, Mohammad Reza Kakoee, Luca Benini, Siamak Mohammadi, Naser Yazdani
10:50 - 11:10 COFFEE BREAK
11:10 - 11:55 KEYNOTE (Auditorium) -- The Homogeneity of Architecture in a Heterogeneous world
John Goodacre, ARM, Cambridge, UK
Chair: Andy Pimentel, University of Amsterdam, NL
11:55     END OF THE SESSIONS
  AFTERNOON: SOCIAL EVENT - BOAT TOUR and BEACHNOTE - Yale Patt, University of Texas at Austin, US
TUESDAY JULY 17, 2012
8:30 - 9:30 KEYNOTE (Auditorium) -- It's About Time 
Edward A. Lee, University of California, Berkeley, US
Chair: John McAllister, Queen's University of Belfast, UK
9:30 - 9:45 COFFEE BREAK
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9:45 - 11:00   SESSION: Domain-Specific Architectures 9:45 - 11:00   SPECIAL SESSION: Programming Paradigms For Reconfigurable Multicore Embedded Systems 9:45 - 11:00   SPECIAL SESSION: Cyber-Physical Systems
Chair: Luigi Carro, UFRGS, BR Chairs: Diana Gohringer, Karlsruhe Institute of Technology, DE
             Pedro Diniz, INESC-ID, PT
Chair: Andreas Herkersdorf, TU Muenchen, DE
9:45 - 10:05 35 Architecture-Level Fault-Tolerance for Biomedical Implants 9:45 - 10:05 ** Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures 9:45 - 10:05 ** Predictable Dynamic Embedded Data Processing
Robert M. Seepers, Christos Strydis, Georgi N. Gaydadjiev Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hubner, Jurgen Becker, Sebastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire     Marc Geilen, Sander Stuijk, Twan Basten
10:10 - 10:30 40 Reconfigurable Miniature Sensor Nodes for Condition Monitoring 10:10 - 10:30 52 Adaptive Reinforcement Learning Method for Networks-on-Chip 10:10 - 10:30 ** Efficient Computing in Cyber-Physical Systems
Teemu Nylanden, Jani Boutellier, Karri Nikunen, Jari Hannuksela, Olli Silven Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Pasi Liljeberg Peter Marwedel, Michael Engel
10:35 - 10:55 75 Counting Stream Registers: An Efficient and Effective Snoop Filter Architecture 10:35 - 10:55 ** Adaptive Processor Architecture 10:35 - 10:55 ** Is Time Predictability Quantifiable?
Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne Michael Huebner, Diana Goehringer, Carsten Tradowky, Joerg Henkel, Jčrgen Becker Martin Schoeberl
11:00 - 11:15 COFFEE BREAK
11:15 - 12:30   SESSION: Dataflow Application Synthesis 11:15 - 12:30   SPECIAL SESSION: Programming Paradigms For Reconfigurable Multicore Embedded Systems 11:15 - 12:30   SPECIAL SESSION: Cyber-Physical Systems
Chair: Juergen Teich, University of Erlangen-Nuremberg, DE Chairs: Diana Gohringer, Karlsruhe Institute of Technology, DE
             Pedro Diniz, INESC-ID, PT
Chair: Marc Geilien, Eindhoven University of Technology, NL
11:15 - 11:35 55 Design Space Exploration in Application-Specific Hardware Synthesis for Multiple Communicating Nested Loops 11:15 - 11:35 ** Adaptive dynamic memory allocators by estimating application workloads 11:15 - 11:35 ** Model-Driven Robot-Software Design using integrated Models and Co-Simulation
Rosilde Corvino, Abdoulaye Gamatie, Marc Geilen, Lech Jozwiak Ioannis Koutras, Alexandros Bartzas, Dimitrios Soudris   Jan F. Broenink, Yunyun Ni
11:40 - 12:00 71 Automatic FPGA Synthesis of Memory Intensive C-based Kernels 11:40 - 12:00 ** Hardware/Software Specialization Through Aspects: The LARA Approach 11:40 - 12:00 *** Multicore Enablement for Cyber Physical Systems
Matthew Milford, John McAllister Joao M. P. Cardoso, Tiago Carvalho, Joao Teixeira, Pedro C. Diniz, Fernando Goncalves, Zlatko Petrov Andreas Herkersdorf
12:05 - 12:25 45 Throughput Driven Transformations of Synchronous Data Flows for Mapping to Heterogeneous MPSoCs 12:05 - 12:25 ** From Scilab to Multicore Embedded Systems: Algorithms and Methodologies 12:05 - 12:25 *** Instrumentation Techniques for Cyber‐Physical Systems Using the Targeted Dataflow Interchange Format
Anastasia Stulova, Rainer Leupers, Gerd Ascheid George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Goehringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Huebner, Timo Stripf, Oliver Oey, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas Shuvra S. Bhattacharyya
12:30 - 12:40 COFFEE BREAK
12:40 - 13:40 PANEL
13:40     END OF THE SESSIONS
  AFTERNOON: SOCIAL EVENT - TRIP TO PSILIAMOS
WEDNESDAY JULY 18, 2012
8:30 - 9:15 KEYNOTE (Auditorium) -- Maximum Performance Computing for Exascale Applications
Oskar Mencer, Maxeler Technologies, London, UK
Chair: Stephan Wong, Delft University of Technology, NL
9:15 - 9:30 COFFEE BREAK
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9:30 - 10:45   SESSION: Dataflow Analysis 9:30 - 10:45   SPECIAL SESSION: FPGA-Based Hardware Emulation 9:30 - 10:45   SPECIAL SESSION: Cyber-Physical Systems
Chair: John McAllister, Queen's University of Belfast, UK Chair: Holger Blume, Leibniz University Hannover, DE Chair: Jan F. Broenink, University of Twente, NL
9:30 - 9:50 7 K-Periodic Schedules for Evaluating the Maximum Throughput of a Synchronous Dataflow Graph 9:30 - 9:50 *** BEE Technology Overview 9:30 - 9:50 ** Challenges in Automotive Cyber-physical Systems Design
Bruno Bodin, Alix Munier-Kordon, Benoit Dupont de Dinechin Joseph Rothman, Chen Chang Dip Goswami, Reinhard Schneider, Alejandro Masrur, Martin Lukasiewycz, Samarjit Chakraborty, Harald Voit, Anuradha Annaswamy
9:55 - 10:15 12 Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph 9:55 - 10:15 38 An FPGA-Accelerated Testbed for Hardware Component Development in MIMO Wireless Communication Systems 9:55 - 10:15 ** A Co-simulation Approach for System-Level Analysis of Embedded Control Systems
Karol Desnos, Maxime Pelcat, Jean-Francois Nezan, Slaheddine Aridhi Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr Michael Glass, Jurgen Teich, Liyuan Zhang
10:20 - 10:40 53 Out-Of-Order Execution of Synchronous Data-Flow Networks 10:20 - 10:40 ** An FPGA-based Prototyping Method for Verification, Characterization and Optimization of LDPC Error Correction Systems 10:20 - 10:40 ** Efficient Hardware Implementation of Data-Flow Parallel Embedded Systems
Daniel Baudisch, Jens Brandt and Klaus Schneider Panagiotis Sakellariou, Ioannis Tsatsaragkos, Nikolaos Kanistras, Ahmed Mahdi, Vassilis Paliouras Patrice Quinton, Anne-Marie Chana, Steven Derrien
10:45 - 11:00 COFFEE BREAK
11:00 - 12:15   SESSION: Embedded Processor Design 11:00 - 12:15   SPECIAL SESSION: FPGA-Based Hardware Emulation 11:00 - 12:15   SESSION:  ESL Tools & Methods
Chair: Stephan Wong, Delft University of Technology, NL Chair: Holger Blume, Leibniz University Hannover, DE Chair: Timo Hamalainen, Tampere University of Technology, FI
11:00 - 11:20 21 An Efficient Asymmetric Distributed Lock for Embedded Multiprocessor Systems 11:00 - 11:20 80 A Quantitative Analysis of Fixed-Point LDPC-Decoder Implementations using Hardware-Accelerated HDL Emulations 11:00 - 11:20 57 TaBit: a Framework for Task Graph to Bitstream Generation
Jochem H. Rutgers, Marco J.G. Bekooij, Gerard J.M. Smit Matthias Korb, Tobias G. Noll Alessandra Bonetto, Andrea Cazzaniga, Gianluca C. Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio
11:25 - 11:45 51 Simultaneous Reconfiguration of Issue-width and Instruction Cache for a VLIW Processor 11:25 - 11:45 59 An FPGA-based Probability-aware Fault Simulator 11:25 - 11:45 41 System-on-Chip deployment with MCAPI abstraction and IP-XACT metadata
Fakhar Anjam, Stephan Wong, Luigi Carro, Gabriel L. Nazar, Mateus B. Rutzig David May, Walter Stechele Lauri Matilainen, Lasse Lehtonen, Joni-Matti Maatta, Erno Salminen, Timo D. Hamalainen
11:50 - 12:10 70 Energy Efficient Stream-based Configurable Architecture for Embedded Platforms 11:50 - 12:10 79 Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems 11:50 - 12:10 68 Efficient System Design using the Statistical Analysis of Architectural Bottlenecks Methodology
Frederico Pratas, Pedro Tomas, Pedro Trancoso, Leonel Sousa Paolo Meloni, Sebastiano Pomata, Luigi Raffo, Roberta Piscitelli, Andy D. Pimentel Manish Arora, Feng Wang, Bob Rychlik, Dean M. Tullsen
12:15 - 12:30 COFFEE BREAK
12:30 - 13:30 PANEL
13:30 - 13:45 CLOSING (Auditorium)
Georgi Gaydadjiev, Chalmers University of Technology, SE
13:45     END OF THE CONFERENCE
  EVENING: SOCIAL EVENT - CONFERENCE DINNER
THURSDAY JULY 19, 2012
  MORNING-AFTERNOON: SOCIAL EVENT - HIKING ON THE MOUNTAINS