Design of a Flexible High-speed FPGA-based Flow Monitor for Next Generation Networks

John McGlone1,  Michaela Blott2,  Roger Woods1,  Alan Marshall1
1Queen's University Belfast, 2Xilinx


The evolution of new services and the development of next generation networks is placing severe demands on how networks will be created. For example, in order to support emerging services it is clear that a higher degree of monitoring functionality is needed within networks. One approach is to use Field Programmable Gate Array (FPGA) technology to create a monitoring solution with greater programmability and real-time performance, thereby allowing monitoring to be implemented dynamically and at the high transmission rates required. This paper presents a novel FPGA-based, programmable IP flow monitor that permits various forms of network monitoring functionality, specifically monitoring of different classes of traffic, to be performed. A key aspect was to address the traditionally long design times, through the use of a new, experimental, high-level design flow called Packet Xpress; this allows the monitoring functions to be quickly implemented and altered, providing a twentyfold speed-up in design time. The monitor has been implemented on a Xilinx Virtex-5 based ML506 board and verified in hardware using real Internet traffic traces. The platform allowed us to experiment with various monitoring functions and establish their resource requirements.