Code Generation for a Novel STA Architecture by Using Post-Processing Backend

Xiaoyan Jia and Gerhard Fettweis
Technische Universit├Ąt Dresden


Abstract

The Synchronous Transfer Architecture (STA) is a variant of VLIW processor architecture with buffered output port on each Functional Units (FUs) [1]. In this paper a novel code generation for a new STA architecture (Luns-STA) is proposed to improve the code performance. It is implemented by using a post-processing backend, which translates compiled code in RISC-ISA into STA-ISA. According to our studies, post-processing can reduce the execution time by about 30.6% to 55.8% in comparison to the execution time in RISC-ISA. And 25% to 48.4% register file are saved in STA-ISA. And Moreover, the power consumption is greatly reduced concerning the efficient utilization of the STA data paths. And besides the short compilation time the novel approaches are not very difficult to implement.