Embedded Multicore Architectures for LDPC Decoding

Gabriel Falcao1,  Leonel Sousa2,  Vitor SIlva1
1IT/Universidade de Coimbra, 2INESC-ID/IST, TU Lisbon


Abstract

Recently, the development of LDPC decoding solutions has been proposed for a vast set of architectures, ranging from hardware dedicated (VLSI, FPGA) to fully programmable ones (GPU, Cell/B.E.). In this paper we propose an efficient embedded multicore architecture able of performing real-time LDPC decoding. We analyze the main characteristics necessary to achieve a given throughput, and we validate our proposal by using the popular Cell/B.E. architecture from Sony/Toshiba/IBM, which relates very closely with the one here propose. Finally, we compare related art for LDPC decoding on GPUs, ASICs and FPGAs.