AN EFFICIENT REALIZATION OF FORWARD INTEGER TRANSFORM IN H.264/AVC INTRA-FRAME ENCODER

Muhammad Nadeem,  Stephan Wong,  Georgi Kuzmanov
TU Delft


Abstract

The H.264/AVC intra-only frame encoder, for its excellent encoding performance, is well-suited for image/video compression applications such as Digital Still Camera (DSC), Digital Video Camera (DVC), Television Studio Broadcast and Surveillance video. Forward Integer Transform is an integral part of H.264/AVC video encoder. In this paper, for image compression applications running on battery-operated electronic devices (such as DSC), we propose a low-power, area-efficient realization of the forward integer transform. The proposed solution reduces the number of operations by more than 50% (30 vs 64) and consumes significantly less dynamic power when compared with existing state-of-the-art designs for the forward integer transform. For video compression applications such as Television Studio Broadcast or Surveillance videos, where throughput is more important, we propose a low-latency, area-efficient realization of forward integer transform unit in the intra frame processing chain. With the proposed solution, the effective latency for Forward Integer Transform is reduced to zero in the intra frame processing chain, as the processing unit is no longer on the critical path. Moreover, the proposed solution requires half the number of operations for its hardware implementation, when compared with existing state-of-the-art designs for forward integer transforms.