SAMOS Workshop 2009 Special Sessions

The workshop considers state-of-the-art research papers as well as papers on ongoing work with promising preliminary results. Positional and in-depth review papers are also considered. Furthermore, the workshop covers additional topics compared to IC-SAMOS that are complementary to processing and necessary to build embedded systems, e.g., sensor systems. In 2009, we intend to have three special sessions focusing on important aspects of embedded systems. They are described below.

Special Session 1:
Instruction-set Customization

Session Chair: Carlo Galuzzi, TU Delft, NL

Over the last years, we have witnessed the increased use of customizable processors. These processors can be tuned and/or extended to meet specific requirements and to achieve a balance between performance, power, hardware resources and time-to-market. The problems involved are numerous and they tend to have high computational complexity. One of the main approaches is the identification of the most suitable instructions to include in the instruction-set.

The customization of an instruction-set via the extension of a basic instruction-set of a processor through specialized instructions presents, between others, many advantages: first, the application code can be more densely encoded; second, the total number of instructions that have to be executed may be reduced which turns into a lower power consumption, and third, the performance of an application can be improved by using the customized instructions.

This special session would like to present new ideas for the partial and complete customization of instruction-sets through the identification of specialized instructions for a given application or domain of applications.

Special Session 2:
The Future of Reconfigurable Computing and Processor Architectures

Session Chairs: Luigi Carro, UFRGS, BR and Stephan Wong, TU Delft, NL

As technology scales up, the design productivity slows down and new approaches must be sought after to reach (or bridge the gap towards) the design productivity that is nowadays common in general-purpose processor design and application development. New tools, technologies, languages, operating systems, and design approaches are likely to be needed. Nowadays, extra transistors are utilized for acceleration purposes (next to prototyping circuits), like they have been used in the past for floating-point operations, and it is today for the case of special blocks embedded into computer architectures like the MMX, SSE, and GPU.

In this special session, papers can be submitted that add to the discussion on how this symbiosis will evolve, how can general-purpose computing benefit from reconfiguration, how can one generalize current accelerators, and how this all will affect (or not) the way compilers produce code. Moreover, one should look at how technology evolution will cope with current possible show-stoppers, like the communication problem and the interface to the operating system. In this session, we hope to give a glimpse into the future of general-purpose reconfigurable computing.

Special Session 3:
Mastering Cell BE and GPU Execution Platforms

Session Chairs: Ed Deprettere, Leiden University, NL and Anna L. Varbanescu, TU Delft, NL

Both Cell BE-type and GPU processors have emerged as multi-processor platforms that can outperform general purpose multi-core computers in certain application domains. The two architectures are quite different, and by no means interchangeable. GPUs are reminiscent of fine-grained systolic array architectures, while the Cell BE is suitable to execute a set of co-ordinated coarse-grained tasks. By now, enough applications have been mapped on either of these two processors, mostly by hand, that the pros and cons tables can be filled.

The aim of this special session is threefold. First, invite experienced users to exchange their findings. Second, to report on preliminary results concerning model-based programming of these processors. Third, bring to debate early attempts to exploit both architectures in a true heterogeneous parallel system, such as a quadcore with CEll BE and GPU extensions.