Accepted Papers

In the following, we present a preliminary list of the papers accepted for publication in the proceedings of the conference, published by IEEE. The papers will be presented in SAMOS on July 14-17, 2014.

ASAP & MDSE Tracks


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A Run-Time Modulo Scheduling by using a Binary Translation Mechanism
Ricardo Ferreira, Waldir Denver, Monica Pereira, Jorge Quadros, Luigi Carro and Stephan Wong
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An Automotive Specific MILP Model Targeting Power-Aware Function Partitioning
Gregor Walla, André S. Enger, Andreas Barthels, Hans-Ulrich Michel and Andreas Herkersdorf
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An ESL Timing & Power Estimation and Simulation Framework for Heterogeneous SoCs
Kim Grüttner, Philipp A. Hartmann, Tiemo Fandrey, Kai Hylla, Daniel Lorenz, Stefan Stattelmann, Björn Sander, Oliver Bringmann, Wolfgang Nebel and Wolfgang Rosenstiel
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Architectural Low-Power Design Using Transaction-Based System Simulation
Fabian Mischkalla and Wolfgang Mueller
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Asynchronous Parallel Simulation with Transaction Events
Bastian Haetzer and Martin Radetzki
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Characterizing communication behavior of dataflow programs using trace analysis
Jorn Janneck, Simone Casale-Brunet and Marco Mattavelli
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Co-Design of Many-Accelerator Heterogeneous Systems Exploiting Virtual Platforms
Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos and Dimitrios Soudris
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Co-Exploration of NLA kernels and Specification of Compute Elements in Distributed Memory CGRAs
Mahesh Mahadurkar, Farhad Merchant, Arka Maity, Kapil Vatwani, Ishan Munje, Nandhini Gopalan, S K Nandy and Ranjani Narayan
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Combining Application Adaptivity and System-wide Resource Management on Multi-Core Platforms
Giuseppe Massari, Edoardo Paone, Patrick Bellasi, Gianluca Palermo, Vittorio Zaccaria, william fornaciari and Cristina Silvano
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Design Flow of a RVC-CAL Multi-Standard Decoder Implementation*
Carlo Sau, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale-Brunet and Marco Mattavelli
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Design Space Exploration for Fair Resource-Allocated NoC Architectures
Antonis Psathakis, Vassilis Papaefstathiou, Manolis Katevenis and Dionisios Pnevmatikatos
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Dynamic-Vector Execution on a General Purpose EDGE Chip Multiprocessor
Milovan Duric, Oscar Palomar, Aaron Smith, Milan Stanic, Osman Unsal, Adrian Cristal, Mateo Valero, Doug Burger and Alex Veidenbaum
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Efficient End-to-End Latency Distribution Analysis for Probabilistic Time-Triggered Systems
Mark Westmijze, Marco Bekooij and Gerard Smit
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Evaluating Private vs. Shared Last-Level Caches for Energy Efficiency in Asymmetric Multi-Cores
Anthony Gutierrez, Ronald Dreslinski and Trevor Mudge
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Evaluating the Memory System Behavior of Smartphone Workloads
Goran Narancic, Patrick Judd, Di Wu, Islam Atta, Michel elnacouzi, Jason Zebchuck, Natalie Enright, Serag Gadelrab, kyros Kutulakos, Andreas Moshovos and Jorge Albericio
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Evaluation of Message Passing Synchronization Algorithms in Embedded Systems
Lazaros Papadopoulos, Ivan Walulya, Philippas Tsigas, Dimitrios Soudris and Brendan Barry
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Extended Performance Analysis of the Time Predictable On-demand Coherent Data Cache for Multi- and Many-core Systems
Arthur Pyka, Mathias Rohde and Sascha Uhrig
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Fast Dynamic Binary Rewriting for Flexible Thread Migration on Shared-ISA Heterogeneous MPSoCs
Giorgis Georgakoudis, Dimitrios Nikolopoulos, Hans Vandierendonck and Spyros Lalis
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GPGPU Workload Characteristics and Performance Analysis
Sohan Lal, Jan Lucas, Michael Andersch, Mauricio Alvarez-Mesa, Ahmed Elhossini and Ben Juurlink
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Highly-Parallel Special-Purpose Multicore Architecture for SystemC/TLM Simulations
Nicolas Ventroux, Julien Peeters, Tanguy Sassolas and James C. Hoe
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Memory Sharing Techniques for Multi-standard High-throughput FEC Decoder
Zhenzhi Wu and Dake Liu
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Micro-architectural Simulation of In-order and Out-of-order ARM Microprocessors with gem5
Fernando Endo, Damien Couroussé and Henri-Pierre CHARLES
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Modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors
Karel De Vogeleer, Gerard Memmi, Pierre Jouvelot and Fabien Coelho
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MPSoCBench: A Toolset for MPSoC System Level Evaluation*
Liana Duenha, Rodolfo Azevedo, Marcelo Guedes, Matheus Boy and Henrique Almeida
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Multi-FPGA Prototyping Board Issue: the FPGA I/O Bottleneck
Qingshan TANG
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On Tokens and Signals: Bridging the Semantic Gap between Dataflow Models and Hardware Implementations
Stavros Tripakis, Rhishikesh Limaye, Kaushik Ravindran and Guoqiang Wang
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Performance Evaluation of the Intel Xeon Phi Manycore Architecture Using Parallel Video-Based Driver Assistance Algorithms
Oliver Jakob Arndt, Daniel Becker, Florian Giesemann, Guillermo Payá Vayá, Christopher Bartels and Holger Blume
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Pre-architectural Performance Estimation for ASIP Design Based on Abstract Processor Models
Juan Fernando Eusse, Christopher Williams, Luis Gabriel Murillo, Rainer Leupers and Gerd Ascheid
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Ranking Software Components Using a Modified PageRank Algorithm Including Safety Aspects*
Dominik Reinhardt
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Resource Conscious Prefetching for Irregular Applications in Multicores
Muneeb Khan and Erik Hagersten
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Robustness Analysis of Multiprocessor Schedules
Shreya Adyanthaya, Zhihui Zhang, Marc Geilen, Jeroen Voeten, Twan Basten and Ramon Schiffelers
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RuRot: Run-time Rotatable-expandable Partitions for Efficient Mapping in CGRAs
Syed Mohammad Asad Hassan Jafri, Guilermo Serrano, Junaid Iqbal, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Juha Plosila and Hannu Tenhunen
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Software-controlled Processor Stalls for Time and Energy Efficient Data Locality Optimization
Philippe Clauss, Imen Fassi and Alexandra Jimborean
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Speculative Synchronization for Coherence-free Embedded NUMA Architectures
Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy and Iris Bahar
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Synthesis of Instruction Extensions on HyperCell, a Reconfigurable Datapath
Kavitha Madhu, Saptarsi Das, Madhava Krishna, Nalesh S, S K Nandy and Ranjani Narayan
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Variable Length Instruction Compression on Transport Triggered Architectures
Janne Helkala, Timo Viitanen, Pekka Jääskeläinen, Heikki Kultala, Tommi Zetterman, Heikki Berg and Jarmo Takala
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WCET-aware Scheduling Optimizations for Multi-Core Real-Time Systems
Timon Kelter, Peter Marwedel and Hendrik Borghorst

Special Session on Brain-targeted and brain-inspired computing


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An analysis on dynamics of CA3b in Hippocampus*
Nikitas Dimopoulos and Babak Keshavarz-Hedayati
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Neural Connectivity Assessment for Epileptic Seizure Prevention: Parallelizing the Generalized Partial Directed Coherence on Many-Core Platforms
Georgios Georgis, Dionysios Reisis, Panagiotis Skordilakis, Konstantinos Tsakalis, Ashfaque Bin Shafique, George Lentaris, and George Chatzikonstantis
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Optimal Mapping of Inferior Olive Neuron Simulations on the Single-Chip Cloud Computer
Dimitrios Rodopoulos, George Chatzikonstantis, Andreas Padelopoulos, Chris De Zeeuw, and Christos Strydis